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A module generator for variable-precision multiplier core with error compensation for low-power DSP applications  

Hwang, Seok-Ki (금오공과대학교 전자공학과 VLSI 설계 연구실)
Lee, Jin-Woo (금오공과대학교 전자공학과 VLSI 설계 연구실)
Shin, Kyung-Wook (금오공과대학교 전자공학과 VLSI 설계 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.30, no.2A, 2005 , pp. 129-136 More about this Journal
Abstract
A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.
Keywords
Multiplier; Multiplier Generator; Booth multiplier; Truncation multiplier; IP core;
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