• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.323-324
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• 2015

Recently, asymmetrical cascaded H-bridge multilevel inverter started to be highlighted as an alternative for the symmetrical cascaded H-bridge. The topology has a small number of part count compared to the symmetrical with higher number of levels. However, it has a drawback of the modulation index limitation which is relatively higher than its symmetrical counterpart, which causes a necessity of an extra voltage pre-regulator. In this paper, the single-sourced pre-regulator is unified with an inner single switch DC/DC converter isolated by coupled inductor. It leads to cost and size reduction. The proposed topology is verified using simulation results.

• Journal of Power Electronics
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• v.17 no.1
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• pp.76-87
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• 2017

Finite-set predictive current control (FS-PCC) is advantageous for power converters due to its high dynamic performance and has received increasing interest in multilevel inverters. Among multilevel inverter topologies, the cascaded H-bridge (CHB) inverter is popular and mature in the industry. However, a main drawback of FS-PCC is its large computational burden, especially for the application of CHB inverters. In this paper, an FS-PCC method based on a deadbeat solution for three-phase zero-common-mode-voltage CHB inverters is proposed. In the proposed method, an inverse model of the load is utilized to calculate the reference voltage based on the reference current. In addition, a cost function is directly expressed in the terms of the voltage errors. An optimal control actuation is selected by minimizing the cost function. In the proposed method, only three instead of all of the control actuations are used for the calculations in one sampling period. This leads to a significant reduction in computations. The proposed method is tested on a three-phase 5-level CHB inverter. Simulation and experimental results show a very similar and comparable control performance from the proposed method compared with the traditional FS-PCC method which evaluates the cost function for all of the control actuations.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.332-335
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• 1996

Multilevel voltage source inverters are emerging as a new breed of power inverter options for high power applications. This paper presents a cascade typed multilevel voltage source inverter which has separate de sources for high voltage. This inverter is proposed for flexible ac transmission systems (FACTS) including static var compensator(SVC), series compensation and phase shifting. It can solve the problems of conventional transformer-based multipulse inverters and the problems of multilevel diode-clamped inverters. To show the superiority of multilevel cascaded inverter, simulation results are discussed in detail.

• Journal of Power Electronics
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• v.16 no.2
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• pp.512-521
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• 2016

Cascaded H-bridge multilevel (CHBML) inverters usually include a large number of isolated dc-voltage sources. Some faults in the dc-voltage sources result in unequal cell dc voltages. Unfortunately, the conventional phase-shifted carrier (PSC) PWM method that is widely used for CHBML inverters cannot eliminate low frequency sideband harmonics when the cell dc voltages are not equal. This paper analyzes the principle of sideband harmonic elimination, and proposes an improved PSCPWM that can eliminate low frequency sideband harmonics under the condition of unequal dc voltages. In order to calculate the carrier phases, it is necessary to solve transcendental equations for low frequency sideband harmonic elimination. Therefore, an approach based on the artificial bee colony (ABC) algorithm is presented in this paper. The proposed PSCPWM method enhances the reliability of CHBML inverters. The proposed PSCPWM is not limited to CHBML inverters. It can also be applied to other types of multilevel inverters. Simulation and experimental result obtained from a prototype CHBML inverter verify the theoretical analysis and the achievements made in this paper.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.5
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• pp.376-380
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• 2010

This paper presents a circuit configuration of multilevel inverter to increase the number of output voltage levels by using conventional 5-level inverters connected in series. Most of all it can maximize the number of output voltage levels by employing input voltage sources, which have the power of five. When it synthesizes the same number of output voltage levels, the proposed inverter can save the number of switching devices compared with the conventional cascaded H-bridge cell inverter. So it can reduce the size, cost, power consumption of the system. We implemented computer-aided simulation and experiments for a 25-level inverter employing two 5-level inverters.

• Journal of Power Electronics
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• v.12 no.4
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• pp.578-586
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• 2012

In this paper a single-phase Cascaded H-Bridge (CHB) inverter for photovoltaic (PV) applications is presented. Based on the presented mathematical analysis, a novel controller is introduced which adjusts the inverter power factor (PF) and manipulates the distribution of the reactive power between the cells to enhance the operating range of the CHB inverter. The adopted control strategy enables tracking of the maximum power point (MPP) of distinct PV strings and allows independent control of the dc-link voltages. The proposed controller also enables the inverter to operate under heavily unbalanced PV conditions. The performance of the CHB inverter and the proposed controllers are evaluated in the PSCAD/EMTDC environment. A seven-level CHB-based grid connected laboratory prototype is also utilized to verify the system performance.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2139-2149
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• 2016

In this study, a new type of cascaded modular multilevel inverters (CMMLIs) is presented which is able to produce a considerable number of output voltage levels with a reasonable number of components. Accordingly, each series stage of the proposed CMMLI is comprised of two same basic units that are connected with each other through two unidirectional power switches without aiming any of the full H-bridge cells. In addition, since the potentiality for generating a higher number of output voltage levels in CMMLIs hinges on the magnitude of the dc voltage sources used in each series unit, in the rest of this paper, four different algorithms for determining an appropriate value for the dc sources' magnitude are also presented. In the following, a comprehensive topological analysis between some CMMLI structures reported in the literature and proposed structure along with several simulation and experimental results will be also given to validate the lucrative benefits and viability of the proposed topology.

• Journal of Electrical Engineering and Technology
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• v.13 no.4
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• pp.1528-1538
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• 2018

In this paper, configuration of $1-{\phi}$ seven-level boost DC-link cascade based reversing voltage multilevel inverter (BDCLCRV MLI) is proposed for uninterrupted power supply (UPS) applications. It consists of three level boost converter, level generation unit and full bridge circuit for polarity generation. When compared with conventional boost cascaded H-bridge MLI configurations, the proposed system results in reduction of DC sources, reduced power switches and gate drive requirements. Inverter switching is accomplished by providing appropriate switching angles that is generated by any optimization switching angle techniques. Here, round modulation control (RMC) method is taken as the optimization method and switching angles are derived and the same is compared with various switching angles methods i.e., equal-phase (EP) method, and half-equal-phase (HEP) method which results in improved quality of obtained AC power with lowest total harmonic distortion (THD). Reduction in DC sources and switch count makes the system more cost effective. A simulation and prototype model of $1-{\phi}$ seven-level BDCLCRV MLI system is developed and its performance is analyzed for various operating conditions.

• Journal of Power Electronics
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• v.14 no.3
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• pp.488-498
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• 2014

This paper presents an implementation of selective harmonic elimination (SHE) modulation for a single-phase 13-level transistor-clamped H-bridge (TCHB) based cascaded multilevel inverter. To determine the optimum switching angle of the SHE equations, the Newton-Raphson method is used in solving the transcendental equation describing the fundamental and harmonic components. The proposed SHE scheme used the relationship between the angles and a sinusoidal reference waveform based on voltage-angle equal criteria. The proposed SHE scheme is evaluated through simulation and experimental results. The digital modulator based-SHE scheme using a field-programmable gate array (FPGA) is described and has been implemented on an Altera DE2 board. The proposed SHE is efficient in eliminating the $3^{rd}$, $5^{th}$, $7^{th}$, $9^{th}$ and $11^{th}$ order harmonics, which validates the analytical results. From the results, it can be seen that the adopted 13-level inverter produces a higher quality with a better harmonic profile and sinusoidal shape of the stepped output waveform.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1074-1086
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• 2019

This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.