• Transactions on Electrical and Electronic Materials
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• 제12권2호
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• pp.43-50
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• 2011

Carbon-nanotube metal oxide semiconductor field effect transistor (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16 nm N-type CN-MOSFETs are explored in this paper. The optimum N-type CN-MOSFET device profiles with different number of tubes are identified for achieving the highest on-state to off-state current ratio ($I_{on}/I_{off}$). The influence of substrate voltage on device performance is also investigated in this paper. Tradeoffs between subthreshold leakage current and overall switch quality are evaluated with different substrate bias voltages. Technology development guidelines for achieving high-speed, low-leakage, area efficient, and manufacturable carbon nanotube integrated circuits are provided.

• ETRI Journal
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• 제32권4호
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• pp.530-539
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• 2010

As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits, quantum mechanical effects are expected to become more and more important. Accurate quantum transport simulators are required to explore the essential device physics as a design aid. However, because of the complexity of the analysis, it has been necessary to simulate the quantum mechanical model with high speed and accuracy. In this paper, the modeling of double gate MOSFET based on an adaptive neuro-fuzzy inference system (ANFIS) is presented. The ANFIS model reduces the computational time while keeping the accuracy of physics-based models, like non-equilibrium Green's function formalism. Finally, we import the ANFIS model into the circuit simulator software as a subcircuit. The results show that the compact model based on ANFIS is an efficient tool for the simulation of nanoscale circuits.

• 전기전자학회논문지
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• 제19권2호
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• pp.232-236
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• 2015

Super-junction trench MOSFET (SJ TMOSFET) devices are well known for lower specific on-resistance and high breakdown voltage (BV). For a conventional power MOSFET (metal-oxide semiconductor field-effect transistor) such as trench double-diffused MOSFET (TDMOSFET), there is a tradeoff relationship between specific on-state resistance and breakdown voltage. In order to overcome the tradeoff relationship, a SJ TMOSFET structure is suggested, but sensing the temperature distribution of TMOSFET is very important in the application since heat is generated in the junction area affecting TMOSFET. In this paper, analyzing the temperature characteristics for different number bonding for SJ TMOSFET with an embedded temperature sensor is carried out after designing the diode temperature sensor at the surface of SJ TMOSFET for the class of 100 V and 100 A for a BLDC motor.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.20-27
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• 2010

Modeling is essential to simulate the operation of integrated circuit (IC) before its fabrication. Seeing a large number of Metal-Oxide-Silicon Field-Effect-Transistor (MOSFET) models available, it has become important to understand them and compare them for their pros and cons. The task becomes equally difficult when the complexity of these models becomes very high. The paper reviews the mainstream models with their physical relevance and their comparisons. Major short-channel and quantum effects in the models are outlined. Emphasis is set upon the latest compact models like BSIM, MOS Models 9/11, EKV, SP etc.

• 한국정보통신학회논문지
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• 제10권2호
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• pp.303-307
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• 2006

본 논문에서는 게이트길이가 $0.9{\mu}m,\;0.1{\mu}m$를 갖는 p형 SiGe MOSFET에 대한 전기적 특성들을 TCAD 시뮬레이터를 이용하여 연구하였다. 또한 온도 300K와 77K일 때 2개의 캐리어 전송모델(하이드로 다이나믹 모델과 드리프트-확산 모델)을 사용하여 전기적 특성들을 비교 분석하였다. 본 논문에서는 드리프트-확산 모델보다는 하이드로 다이나믹 모델을 사용하였을 때 드레인 전류가 더 많이 흐름을 알 수 있었다. 게이트 길이가 $0.9{\mu}m$일 때 문턱 전압은 온도가 300K, 77K에서 각각 -0.97V와 -1.15V의 값을 가짐을 알수 있었다. 또한 게이트 길이가 $0.1{\mu}m$일 때 문턱전압들은 게이트길이가 $0.9{\mu}m$일 때의 값과 거의 같음을 알 수 있었다.

• 한국정보통신학회논문지
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• 제6권1호
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• pp.103-108
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• 2002

MOSFET는 전력감소, 도핑농도 증가, 캐리어 속도 증가를 위해서 많은 변화를 가져왔다. 이러한 변화를 받아들이기 위해서, 채널의 길이와 공급전압이 감소해야만하며, 그것으로 인해 소자가 더욱 작아지게 되었다. 현존하고 있는 시뮬레이션 프로그램은 많은 기술자와 과학자들에 의해 개발되어졌다. 본 논문에서는 상용화되어지고 있는 두 가지 시뮬레이터인 Micro-tec과 ISE-TCAD을 사용하여 나노 구조 소자를 시뮬레이션하여 비교하였다. 소자의 게이트 길이(Lg)는 180nm를 사용하였다. 두 시뮬레이터를 사용하여 MOSFET의 특성과 I-V 곡선 및 전계에 대해서 비교 분석하였다.

• 한국전기전자재료학회논문지
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• 제26권4호
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• pp.284-288
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• 2013

Power MOSFETs(Metal Oxide Semiconductor Field Effect Transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. We have experimental results and explanations on the doping profile dependence of the electrical behavior of the vertical MOSFET. The device is fabricated as $8.25{\mu}m$ cell pitch and $4.25{\mu}m$ gate width. The performances of device with various p base doping concentration are compared at Vth from 1.77 V to 4.13 V. Also the effect of the cell structure on the on-resistance and breakdown voltage of the device are analyzed. The simulation results suggest that the device optimized for various applications can be further optimized at power device.

• 전기전자학회논문지
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• 제21권1호
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• pp.96-99
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• 2017

본 연구에서는 금속-산화막-반도체 전계효과 트랜지스터의 불순물 분포변동 효과에 미치는 halo 및 LDD 이온주입 공정의 영향을 3차원 소자 시뮬레이션을 통하여 확인하였다. 정확한 시뮬레이션 계산을 위해 kinetic monte carlo 모델을 적용하여 불순물 입자와 결함 낱낱의 거동을 계산하는 원자단위 시뮬레이션을 수행하였다. 문턱전압 및 on-current의 산포를 통해 확인한 결과 halo 이온주입 공정이 LDD 이온주입 공정보다 문턱전압 산포의 경우 약 6.45배 그리고 on-current 산포의 경우 2.46배 더 큰 영향을 미치는 특성을 확인하였다. 그리고 문턱전압과 on-current 산포를 히스토그램으로 나타내어 그 산포를 정규분포로 확인하였다.

• Transactions on Electrical and Electronic Materials
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• 제17권5호
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• 전력전자학회논문지
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• 제22권2호
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• pp.181-184
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• 2017

This study analyzes the turn-on and turn-off transients of a metal-oxide-semiconductor field-effect transistor (MOSFET) with high-switching frequency systems. In these systems, the voltage distortion becomes serious at the output terminal of a Vienna rectifier by the turn-off delay of the MOSFET. The current has low-order harmonics through this voltage distortion. This paper describes the transient of the turn-off that causes the voltage distortion. The algorithm for reducing the sixth harmonic using a proportional-resonance controller is proposed to improve the current distortion without complex calculation for compensation. The reduction of the current distortion by high-switching frequency is verified by experiment with the 2.5-kW prototype Vienna rectifier.