• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.164-169
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• 2008

The effects of the antisite related defects on the electronic structure of silica and the gate leakage current have been investigated using first-principles calculations. Energy levels related to the antisite defects in silicon dioxide have been introduced into the bandgap, which are nearly 2.0 eV from the top of the valence band. Combining with the electronic structures calculated from first-principles simulations, tunneling currents through the silica layer with antisite defects have been calculated. The tunneling current calculations show that the hole tunneling currents assisted by the antisite defects will be dominant at low oxide field whereas the electron direct tunneling current will be dominant at high oxide field. With increased thickness of the defect layer, the threshold point where the hole tunneling current assisted by antisite defects in silica is equal to the electron direct tunneling current extends to higher oxide field.

• 전자공학회논문지 IE
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• 제44권2호
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• pp.14-20
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• 2007

본 논문에서는 개선된 성능을 갖는 4치 D-플립플롭을 제안하였다. 제안된 4치 D 플립플롭은 뉴런모스를 기반으로 바이어스 인버터, 온도계 코드 출력회로, EX-OR 게이트, 전달 게이트를 이용하여 4치 항등 논리회로(Identity logic circuit)를 구성하고, 이를 2진의 RS 래치 회로와 결합하여 설계하였다. 설계된 회로들은 3.3V 단일 공급 전원에서 $0.35{\mu}m$ 1-poly 6-metal COMS 공정 파라미터 표준조건에서 HSPICE를 사용하여 모의실험 하였다. 모의실험 결과, 본 논문에서 제안된 4치 D 플립플롭은 100MHz 전후까지의 빠른 동작속도로 측정되었으며 PDP(Power dissipation-delay time product)와 FOM(Figure of merit)은 각각 59.3pJ과 33.7로 평가되어졌다.

• 마이크로전자및패키징학회지
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• 제12권1호
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• pp.59-63
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• 2005

금속-강유전체-반도체 전계효과 트랜지스터 (MFS/MFISFET)의 동작 특성을 technology computer-aided design (TCAD)과 simulation program with integrated circuit emphasis (SPICE)를 결합하여 전산모사하는 방법을 제시하였다. 복잡한 강유전체의 동작 특성을 수치해석을 이용하여 해석한 다음, 이를 이용하여 금속-강유전체-반도체 구조에서 반도체 표면에 인가되는 표면 전위를 계산하였다. 계산된 TCAD 변수인 표면 전위를 전계효과 트랜지스터의 SPICE 모델에서 구한 표면 전위와 같다고 보고게이트 전압에 따른 전류전압 특성을 구할 수 있었다. 이와 같은 방법은 향후 MFS/MFISFET를 이용한 메모리소자의 집적회로 설계에 매우 유용하게 적용될 수 있을 것이다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1284-1287
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• 2005

Peripheral pentacene region gives a significant influence on C-V characteristics of metal-oxide-pentacene capacitor structure. When the gate voltage goes toward negative, the effect of peripheral pentacene region becomes larger. Remaining gate DC bias constant and changing small signal frequency, the capacitance of peripheral pentacene changes along with frequency so that the total capacitance value also changes. The influence of peripheral pentacene region should be removed to measure accurate C-V characteristics, because it is hard to take into account the effect of the region quantitatively. After removing the influence of peripheral pentacene region, acceptor concentration, flat band voltage and depletion width of pentacene thin film are extracted from an accurate C-V curve as $1.58{\times}10^{17}cm^{-3}$, -1.54 V and 39.4 nm, respectively.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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• pp.122-126
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• 1989

A composite polycide struoture consisting of refractory metal and noble metal silicide film on top of polysilicon bas been considered as a replacement for polysilicon as a gate electrode and Interconnect line in MOSFET integrated circuits. In this paper presents divice characteristics of NOS with $TiSi_2/n^+$polyoide and $CoSi_2/n^+$polycide gate. Also, evaporated Ti,Co films on polysilicon has been annealed by RTA and furnace annealing in $N_2$ abient at temperature of $400^{\circ}C-1000^{\circ}C$. The Ti-,Co-silioide formation is characterized by 4-point probe, silicide growth rate and Its reproductivity bas been examined by SEM.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권3호
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• pp.189-198
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• 2006

A new analytical model has been proposed for predicting the sheet carrier density of Metal insulator Semiconductor High Electron Mobility Transistor (MISHEMT). The model takes into account the non-linear relationship between sheet carrier density and quasi Fermi energy level to consider the quantum effects and to validate it from subthreshold region to high conduction region. Then model has been formulated in such a way that it is applicable to MESFET/HEMT/MISFET with few adjustable parameters. The model can also be used to evaluate the characteristics for different gate insulator geometries like T-gate etc. The model has been extended to forecast the drain current, conductance and high frequency performance. The results so obtained from the analysis show excellent agreement with previous models and simulated results that proves the validity of our model.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.248-248
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• 2010

CMOS 축소화가 32nm node를 넘어서 지속적으로 진행되기 위하여 FinFET, Surround Gate and Tri-Gate와 같은 Fully Depleted 3-Dimensional 소자들이 SCE를 다루기 위해서 많이 제안되어 왔다. 하지만 소자의 축소화를 진행함에 있어서 좁고 균일한 patterning을 형성하는 것과 동시에 낮은 Extension Region과 Contact Region에서의 Series Resistance을 제공하여야 하고 Source/Drain Contact Formation을 확보하여야 한다. 그리고 소자의 축소화가 진행됨으로써 Silicide의 응집현상과 Source/Drain Junction의 누설전류에 대한 허용범위가 점점 엄격해지고 있다. ITRS 2005에 따르면 32nm CMOS에서는 Contact Resistivity가 대략 $2{\times}10-8{\Omega}cm2$이 요구되고 있다. 또한 Three Dimensional 소자에서는 Fin Corner Effect가 Channel Region뿐만 아니라 S/D Region에서도 중대한 영향을 미치게 된다. 따라서 본 논문에서 제시하는 Novel S/D Contact Formation 기술을 이용하여 Self-Aligned Dual/Single Metal Contact을 이루어Patterning에 대한 문제점 해결과 축소화에 따라 증가하는 Contact Resistivity 문제점을 해결책을 제시하고자 한다. 이를 검증하기3D MOSFET제작하고 본 기술을 적용하고 검증한다. 또한 Normal Doping 구조를 가진3D MOSFET뿐만 아니라 SCE를 해결하기 위해서 대안으로 제시되고 있는 SB-MOSFET을 3D 구조로 제작하고, 이 기술을 적용하여 검증한다. 그리고 Silvaco simulation tool을 이용하여 S/D에 Metal이 Contact을 이루는 구조가 Double type과 Triple type에 따라 Contact Resistivity에 미치는 영향을 미리 확인하였고 이를 실험으로 검증하여 소자의 축소화에 따라 대두되는 문제점들의 해결책을 제시하고자 한다.

• 진공이야기
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• 제3권3호
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.