• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.183-186
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• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.171-172
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• 2007

We fabricated the metal-ferroelectric-insulator-semiconductor filed-effect transistors (MFIS-FETs) using the $(Bi,La)_4Ti_3O_{12}\;and\;LaZrO_x$ thin films. The $LaZrO_x$ thin film had a equivalent oxide thickness (EOT) value of 8.7 nm. From the capacitance-voltage (C-V) measurements for an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si MFIS capacitor, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.4 V for the bias voltage sweeping of ${\pm}9V$. From drain current-gate voltage $(I_D-V_G)$ characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) was about 1 V due to ferroelectric nature of BLT film. The drain current-drain voltage $(I_D-V_D)$ characteristics of the fabricated Fe-FETs showed typical n-channel FETs current-voltage characteristics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1657-1662
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• 2014

In this paper, the impact of substrate bias($V_{BS}$) on the zero capacitor RAM(Z-RAM) in n-channel junctionless multiple gate MOSFET(MuGFET) has been analyzed experimentally. Junctionless transistors with fin width of 50nm and 1 fin exhibits a memory window of 0.34V and a sensing margin of $1.8{\times}10^4$ at $V_{DS}=3.5V$ and $V_{BS}=0V$. As the positive $V_{BS}$ is applied, the memory window and sensing margin were improved due to an increase of impact ionization. When $V_{BS}$ is increased from 0V to 10V, not only the memory window is increased from 0.34V to 0.96V but also sensing margin is increased slightly. The sensitivity of memory window with different $V_{BS}$ in junctionless transistor was larger than that of inversion-mode transistor. A retention time of junctionless transistor is better than that of inversion-mode transistor due to low Gate Induced Drain Leakage(GIDL) current. To evaluate the device reliability of Z-RAM, the shifts in the Set/Reset voltages and current were measured.

• Journal of IKEEE
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• v.27 no.4
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• pp.386-390
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• 2023

In this study, we examined the quasi-nonvolatile memory characteristics of silicon nanosheet (SiNS) feedback field-effect transistors (FBFETs) fabricated using a complementary metal-oxide-semiconductor process. The SiNS channel layers fabricated by photoresist overexposure method had a width of approximately 180 nm and a height of 70 nm. The SiNS FBFETs operated in a positive feedback loop mechanism and exhibited an extremely low subthreshold swing of 1.1 mV/dec and a high ON/OFF current ratio of 2.4×10⁷. Moreover, SiNS FBFETs represented long retention time of 50 seconds, indicating the quasi-nonvolatile memory characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.91-96
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• 1992

The nonvolatile SNOSFET EEPROM memory devices with the channel width and iength of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] were fabricated by using the actual CMOS 1 [Mbit] process technology. The charateristics of I$\_$D/-V$\_$D/, I$\_$D/-V$\_$G/ were investigated and compared with the channel width and length. From the result of measuring the I$\_$D/-V$\_$D/ charges into the nitride layer by applying the gate voltage, these devices ere found to have a low conductance state with little drain current and a high conductance state with much drain current. It was shown that the devices of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$] represented the long channel characteristics and the devices of 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] represented the short channel characteristics. In the characteristics of I$\_$D/-V$\_$D/, the critical threshold voltages of the devices were V$\_$w/ = +34[V] at t$\_$w/ = 50[sec] in the low conductance state, and the memory window sizes wee 6.3[V], 7.4[V] and 3.4[V] at the channel width and length of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$], 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$], respectively. The positive logic conductive characteristics are suitable to the logic circuit designing.

• Electrical & Electronic Materials
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• v.16 no.9
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• pp.64.1-64
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• 2003

A metal-ferroelectric [SrBi$_2$Ta$_2$O$\_$9/ (SBT)-high-k-insulator(PrOx)-semiconductor(Si) structure has been fabricated and evaluated as a key part of metal-ferroelectric-insulator-semiconductor-field-effect-transistor MFIS-FET memory, aiming to improve the memory retention characteristics by increasing the dielectric constant in the insulator layer and suppressing the depolarization field in the SBT layer. A 20-nm PrOx film grown on Si(100) showed both a high of about 12 and a low leakage current density of less than 1${\times}$ 10e-8 A/$\textrm{cm}^2$ at 105 MV/cm. A 400-nm SBT film prepared on PrOx/Si shows a preferentially oriented (105) crystalline structure, grain size of about 130 nm and subface roughness of 3.2 nm. A capacitance-voltage hysteresis is confirmed on the Pt/SBT/PrOx/Si diode with a memory window of 0.3V at a sweep voltage width of 12 V. The memory retention time was about 1 104s, comparable to the conventional Pt/SBT/SiO$\_$x/N$\_$y/(SiO$\_$N/)/Si. The gradual change of the capacitance indicates that some memory degradation mechanism is different from that in the Pt/SBT/SiON/Si structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.70-73
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• 2001

MFIS(Metal-ferroelectric-insulator- semiconductor) structures using silicon oxynitride(SiON) buffer layers were fabricatied and demonstrated nonvolatile memory operations. Oxynitride(SiON) films have been formed on p-Si(100) by RTP(rapid thermal process) in O$_2$+N$_2$ ambient at 1100$^{\circ}C$. The gate leakage current density of Al/SiON/Si(100) capacitor was about the order of 10$\^$-8/ A/cm$^2$ at the range of ${\pm}$ 2.5 MV/cm. The C-V characteristics of Al/LiNbO$_3$/SiON/Si(100) capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 24. The memory window width was about 1.2V at the electric field of ${\pm}$300 kV/cm ranges.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.221-224
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• 2000

We have successfully demonstrated metal-ferroel-ectric-insulator-semiconductor (MFIS) devices using Al/LiNbO$_{3}$/SiN/Si structure. The SiN thin films were made into metal -insulator- semiconductor (MIS) devices by thermal evaporation of aluminum source in a dot away on the surface. The interface property of MFIS from 1MHz & quasistatic C-V is good and the memory window width is about 1.5V at 0.2V/s signal voltage sweep rate. The gate leakage current density of MFIS capacitors using a aluminum electrode showed the least value of 1x10$^{-8}$ A/$\textrm{cm}^2$ order at the electric field of 300㎸/cm. And the XRD patterns shows the probability of applications of LN for MFIS devices for FeRAMs on amorphous SiN buffer layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.289.1-289.1
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• 2014

In this study, we made a organic thin film device in MIS(Metal-Insulator-Semiconductor) structure by using PVP (Poly vinyl phenol) as a insulating layer, and CdSe/ZnS nano particles which have a core/shell structure inside. We dissolved PVP and PMF in PGMEA, organic solvent, then formed a thin film through a spin coating. After that, it was cross-linked by annealing for 1 hour in a vacuum oven at $185^{\circ}C$. We operated FTIR measurement to check this, and discovered the amount of absorption reduced in the wave-length region near 3400 cm-1, so could observe decrease of -OH. Boonton7200 was used to measure a C-V relationship to confirm a properties of the nano particles, and as a result, the width of the memory window increased when device including nano particles. Additionally, we used HP4145B in order to make sure the electrical characteristics of the organic thin film device and analyzed a conduction mechanism of the device by measuring I-V relationship. When the voltage was low, FNT occurred chiefly, but as the voltage increased, Schottky Emission occurred mainly. We synthesized CdSe/ZnS and to confirm this, took a picture of Si substrate including nano particles with SEM. Spherical quantum dots were properly made. Due to this study, we realized there is high possibility of application of next generation memory device using organic thin film device and nano particles, and we expect more researches about this issue would be done.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.765-770
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• 2001

Metal-ferroelectric-insulator- semiconductor(MFTS) devices by using rapid thermal annealed (RTA) LiNbO$_3$/AIN/Si(100) structures were successfully fabricated and demonstrated nonvolatile memory operations. Metal-insulator-semiconductor(MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2 V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/$\textrm{cm}^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8 V, 50 % duty cycle) in the 500 kHz.