• 한국산학기술학회논문지
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• 제15권8호
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• pp.5213-5218
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• 2014

유기메모리 제작을 위해 플라즈마 중합법에 의해 절연박막, 터널링 박막을 제작하였고, Au 메모리박막을 이용하여 플로팅게이트형 유기메모리를 제작하였다. 플로팅 게이트형 유기메모리의 메모리층의 전하충전 및 방전에 따른 유기메모리 동작특성을 생각해 보았고, 이를 증명하고자 게이트전압에 따른 히스테리전압 및 메모리전압을 측정하였다. 그 결과 게이트 전압의 인가에 따른 메모리층의 동작 이론을 증명하고자 게이트전압이 증가함에 따른 소스-드레인 전류의 히스테리시스 현상이 심해지는 것을 확인하였고, -60~60[V]전압 인가시 26[V]의 큰 히스테리시스 전압값을 보였다. 또한 게이트 전극에 쓰기전압인가에 따른 현상을 본 결과, 60[V]의 쓰기 전압을 인가하였을 시 13[V]의 memory 전압을 나타내었고, 80[V]의 쓰기전압을 인가하였을 시 18[V]로 memory 전압이 약 40[%] 향상된 수치를 보였다. 이로부터 메모리층의 전하 충전 및 방전에 따른 메모리 동작특성 이론을 실험적으로 검증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권2호
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• pp.125-131
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• 2001

When the program voltage is applied to a word line, a part of the boosted channel charge in inhibited bit lines is lost due to the coupling between the string select line (SSL) and the adjacent word line. This phenomenon causes the program disturbance in the cells connected to the inhibited bit lines. This program disturbance becomes more serious, as the word line pitch is decreased. To reduce the word line coupling, the rising edge of the word-line voltage waveform was changed from a pulse step into a ramp waveform with a controlled slope. The word-line ramping circuit was composed of a timer, a decoder, a 8 b D/A converter, a comparator, and a high voltage switch pump (HVSP). The ramping voltage was generated by using a stepping waveform. The rising time and the stepping number of the word-line voltage for programming were set to $\mutextrm{m}-$ and 8, respectively,. The ramping circuit was used in a 512Mb NAND flash memory fabricated with a $0.15-\mutextrm{m}$ CMOS technology, reducing the SSL coupling voltage from 1.4V into a value below 0.4V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권3호
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• pp.195-203
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• 2005

Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2D numerical simulation tool as the device simulator.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.222-227
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• 2004

The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The MOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell array section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of $5{\mu}C/cm^2$ and SBL capacitance of 40fF is about 700mV at 3.0V operation voltage. That is high compensation method for capacitor size degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than $5{\mu}C/cm^2$.

• 전기의세계
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• 제22권2호
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• pp.45-50
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• 1973

Amorphous semiconducting diodes from As Te Ge systm of which resitivity are 10$^{6}$ -10$^{8}$ .ohm.-cm order, are made and they exhibited several conducting states. A high conductivity, low conductivity and memory state are reported. Temperature dependency of the specimens are widerange. According to the procedure and cooling method, specimens are made easily or not. Threshold voltage of switching and memory diodes is in proportional to compositonal quantity of Arsenic. Threshold voltage is changed widely according to ambient temperature. Threshold voltage of #132 is 620V at 25.deg. C, 70V at 100.deg. C.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1555-1557
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• 2002

We have investigated the precharge type sense amplifier, it is suitable fur voltage sensing in a NOR type single transistor ferroelectric field effect transistor (1T FeFET) memory read operation. The proposed precharge type sense amplifier senses the bit line voltage of 1T FeFET memory. Therefore, the reference celt is not necessary compared to current sensing in 1T FeFET memory, The high noise margin is wider than the low noise margin in the first inverter because requires tile output of precharge type sense amplifier high sensitivity to transition of input signal. The precharge type sense amplifier has very simple structure and can sense the bit line signal of the 1T FeFET memory cell at low voltage.

• 한국정보전자통신기술학회논문지
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• 제9권1호
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• pp.120-131
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• 2016

본 논문에서는 back-gate bias 전압인 VNN (Negative Voltage)을 이용하여 5V의 MV (Medium Voltage) 소자만 이용하여 FN (Fowler-Nordheim) tunneling 방식으로 write하는 MTP cell을 사용하여 512비트 MTP IP를 설계하였다. 사용된 MTP cell은 CG(Control Gate) capacitor, TG(Tunnel Gate) transistor와 select transistor로 구성되어 있다. MTP cell size를 줄이기 위해 TG transistor와 select transistor를 위한 PW(P-Well)과 CG capacitor를 위한 PW 2개만 사용하였으며, DNW(Deep N-Well)은 512bit MTP cell array에 하나만 사용하였다. 512비트 MTP IP 설계에서는 BGR을 이용한 voltage regulator에 의해 regulation된 V1V (=1V)의 전압을 이용하여 VPP와 VNN level detector를 설계하므로 PVT variation에 둔감한 ${\pm}8V$의 pumping 전압을 공급할 수 있는 VPP와 VNN 발생회로를 제안하였다.

• 한국전자통신학회논문지
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• 제11권2호
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• pp.159-164
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• 2016

무선통신시스템은 한정된 에너지를 갖는 배터리를 사용하기 때문에 저전력 회로로 구현되어야 하며, 이를 위하여 주파수와 상관없이 일정한 전력을 나타내는 전류모드 회로가 연구되어왔다. 본 논문에서는 초저전력 동작이 가능하도록 Dynamic Voltage Scaling 전원을 유도하며, 전류모드 신호처리 중 메모리 동작에서 저장된 에너지가 누설되는 Clock-Feedthrough 문제를 최소화하는 전류메모리 회로를 제안한다. $0.35{\mu}m$ 공정의 BSIM3 모델로 Near-threshold 영역의 전원 전압을 사용한 시뮬레이션을 진행한 결과, 1MHz의 스위칭 동작에서 $2{\mu}m$의 메모리 MOS Width, $0.3{\mu}m$의 스위치 MOS Width, $13{\mu}m$의 Dummy MOS Width로 설계할 때, Clock-Feedthrough의 영향을 최소화시킬 수 있었으며 1.2V의 Near-threshold 전원전압에서 소비전력은 $3.7{\mu}W$가 계산되었다.

• E2M - 전기 전자와 첨단 소재
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• 제8권6호
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• pp.727-736
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• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.