• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.1
• /
• pp.79-89
• /
• 2014

It has been an increase in consumers who want a high-capacity and fast speed by the newly diffused mobile device(Smart phones, Ultra books, Tablet PC). As a result, the demand for Flash Memory is constantly increasing. Flash Memory is separated by a NAND-type and NOR-type. NAND-type Flash Memory speed is slow, but price is cheaper than the NOR-type Flash Memory. For this reason, NAND-type Flash Memory is widely used in the mobile market. So Fault Detection is very important for Flash Memory Test. In this paper, Proposed PMBIST for Pattern Test of NAND-type Flash Memory improved Fault detection.

• ETRI Journal
• /
• v.37 no.4
• /
• pp.787-792
• /
• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• ETRI Journal
• /
• v.35 no.5
• /
• pp.808-818
• /
• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.914-917
• /
• 2008

A quad-functional built-in test circuit has been developed for DRAM-frame-memory embedded SOG-LCDs. The quad function consists of memory test, display test, serial transfer test, and parallel transfer test which is the normal operation mode for our SOG-LCD. Results of memory and display tests are shown.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.6
• /
• pp.122-130
• /
• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.

• Journal of Oriental Neuropsychiatry
• /
• v.24 no.1
• /
• pp.27-44
• /
• 2013

Objectives : This study was designed to investigate the effects of Gastrodia elata Blume on the improvement of memory. Methods : This study was a 12 week, double blind, comparative clinical study. There were eligible who worked with a group of healthy seniors, all 60 years of age or older. 50 subjects were randomized either to Gastrodia elata Blume in powder form and steep in hot water or placebo. We measured the faculty of memory by using K-DRS, MMSE-K, Digit Span, Letter Fluency Test, Word List Memory Test, and the Trail Making Test, and after 12 weeks we measured the faculty of memory again using the same methods. Results : Gastrodia elata Blume steeps in the hot water group significantly increased. Initiation, perseveration level, and Memory level of K-DRS and MMSE-K score. There were no considerable differences between three groups in Digit Span and Trail Making Test score. Gastrodia elata Blume group showed significant advances in Letter Fluency Test and recognition of Word List Memory Test. Conclusions : The results suggest that Gastrodia elata Blume may have positive effects on memory improvement and function of the frontal lobe activation.

• Journal of the Korea Convergence Society
• /
• v.11 no.6
• /
• pp.203-208
• /
• 2020

This study examined whether Mild Cognitive Impairment (MCI) is related to the reduction of specific memory among linguistic memory and visuospatial memory, and to identify the most predictive index for discriminating MCI from normal elderly. The subjects were analyzed for 189 elderly (103 healthy elderly, 86 MCI). The verbal memory was used by the Seoul Verbal Learning Test. visuospatial memory was measured using the Rey Complex Figure Test. As a result of multiple logistic regression, verbal memory and visuospatial memory showed significant predictive performance in discriminating MCI from normal elderly. On the other hand, when all the confounding variables were corrected, including the results of each memory test, the predictive power was significant in distinguishing MCI from normal aging only in the immediate recall of verbal memory, and the predictive power was not significant in the immediate recall of visuospatial memory. This result suggests that delayed recall of visuospatial memory and immediate recall of verbal memory are the best combinations to discriminate memory ability of MCI.

• Journal of Microbiology and Biotechnology
• /
• v.23 no.12
• /
• pp.1779-1784
• /
• 2013

Although enzyme-hydrolyzed silk fibroin has been reported to enhance cognitive function before, it has been still unknown which peptides can improve memory. Here we report that amino acid sequences of three novel peptides were identified from fibroin hydrolysate. Fibroin hydrolysate was obtained by hydrolysis with protease after partial hydrolysis with 5M $CaCl_2$. Synthesized peptides derived from these sequences improved scopolamine-induced memory impairments in mice. We confirmed this hydrolysate had effects that improved learning and memory abilities by performing the Rey-Kim test. From this hydrolysate of silk fibroin, amino acid sequences of eight peptides were identified by LC-MS/MS. Three peptides (GAGAGTGSSGFGPY, GAGAGSGAGSGAGAGSGAGAGY, and SGAGSGAGAGSGAGAGSGA) were synthesized to investigate whether they could improve memory. Passive avoidance test and Morris water maze test were performed, and all peptides showed memory-enhancing abilities on scopolamine-induced memory impairments in mice. In this study, we identified three novel peptides that could improve memory, and that silk fibroin hydrolysate was a mixture of various active peptides that could enhance memory.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.12
• /
• pp.61-70
• /
• 2007

The density of Memory has been increased by great challenge for memory technology. Therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip (SOC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. Proposed design doesn't need controls from outside environment, because it integrates into memory. In general, there are a variety of memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme supports the various memory testing process. Moreover, it is able to At-Speed test in a memory module. consequently, the proposed is more efficient in terms of test cost and test data to be applied.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.1
• /
• pp.8-15
• /
• 1993

A concrete disign of memory circuit is presented aiming at the application of sliding diagonal test patterns. A modification of sliding diagonal test pattern includes the complexity reduction from O(n$^{32}$) to O(n) using parallel test memory concept. The control circuit design was based on delay-element, and verified via logic and circuit simulation. Area overhead was evaluated based on physical layout using a 0.7 micron design rule resulting in about 1% area increase for a typical 16Mbit DRAM.