• Journal of the Korean Society for Heat Treatment
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• v.30 no.6
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• pp.251-257
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• 2017

The effect of annealing temperature on the martensitic transformation behavior, tensile deformation chracteristics and shape recovery etc., has been studied in TiNi based shape memory ribbon fabricated by coldrolling of wire. TiNi based shape memory wire (${\phi}=500{\mu}m$) of which structure is intermetallic compound could be cold-rolled without process annealing up to the reduction rate in thickness of 50%, but a few cracks appear in cold-rolled ribbon in the reduction rate in thickness of 65%. The $B2{\rightarrow}R{\rightarrow}B19^{\prime}$ martensitic transformation or $B2{\rightarrow}B19^{\prime}$ martensitic transformation occurs in annealing conditions dissipating lattice defects introduced by coldrolling. However, in case of higher reduction rate or lower annealing temperature, martensitic transformation in cold-rolled and then annealed ribbons does not occur. The maximum shape recovery rate of cold-rolled ribbons with the reduction rate of 35 and 65% could be achieved at annealing temperatures of 250 and $350^{\circ}C$, respectively. The shape recovery rate seems to be related to the stress level of plateau region on stress-strain curve.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.8-15
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• 1993

A concrete disign of memory circuit is presented aiming at the application of sliding diagonal test patterns. A modification of sliding diagonal test pattern includes the complexity reduction from O(n$^{32}$) to O(n) using parallel test memory concept. The control circuit design was based on delay-element, and verified via logic and circuit simulation. Area overhead was evaluated based on physical layout using a 0.7 micron design rule resulting in about 1% area increase for a typical 16Mbit DRAM.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.1
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• pp.30-34
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• 1997

An improved clock-feedthrough compensation scheme for switche dcurrent system is proposed. Both the signal dependent and the constant clock-feedthrough terms are cancelled by using both NMOS and PMOS current samplers and by adopting a source replication technique. The proposed current memory cell was fabricated with 0.6$\mu$m CMOS process. Both experimental and theoretical results on clock-feedthrough error reveal substantial reduction over the existing compensation schemes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.199-203
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• 2017

Mutually-actuated-nano-electromechanical (MA-NEM) memory switches are proposed for scalability improvement. While conventional NEM memory switches have fixed electrode lines, the proposed MA-NEM memory switches have mutually-actuated cantilever-like electrode lines. Thus, MA-NEM memory switches show smaller deformations of beams in switching. This unique feature of MA-NEM memory switches allows aggressive reduction of the beam length while maintaining nonvolatile property. Also, the scalability of MA-NEM memory switches is confirmed by using finite-element (FE) simulations. MA-NEM memory switches can be promising solutions for reconfigurable logic (RL) circuits.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.3
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• pp.151-156
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• 2015

Recently, an embedded flash memory has been widely used for the Internet of Things(IoT). Due to its nonvolatility, economical feasibility, stability, low power usage, and fast speed. With respect to power consumption, the embedded memory system must consider the most significant design factor. The objective of this research is to design high performance and low power NAND flash memory architecture including a dual buffer as a replacement for NOR flash. Simulation shows that the proposed NAND flash system can achieve better performance than a conventional NOR flash memory. Furthermore, the average memory access time of the proposed system is better that of other buffer systems with three times more space. The use of a small buffer results in a significant reduction in power consumption.

• Journal of Korea Multimedia Society
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• v.14 no.1
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• pp.94-102
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• 2011

To alleviate the size and bandwidth requirement in JPEG2000 system, a new Embedded Compression(EC) algorithm with minor image quality drop is proposed. For both random accessibility and low latency, very simple and efficient hadamard transform based compression algorithm is devised. We reduced LL intermediate memory and code-block memory to about half size and achieved significant memory bandwidth reductions(about 52~73%) through proposed multi-mode algorithms, without requiring any modification in JPEG2000 standard algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.37-42
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• 2008

In H.264/AVC decoder, intra predictor, motion compensator, and deblocking filter need to read reference images in external frame memory in decoding process. They read external frame memory very frequently, which lowers system operation speed and increases power consumption. This paper proposes a intra predictor integrated with motion compensator without external frame memory. It achieves power reduction and memory bandwidth minimization by exploiting data reuse of common and repetitive pixels. The proposed infra predictor achieves more than $45%\;{\sim}\;75%$ cycle time reduction compared with conventional intra predictors.

• Transactions of Materials Processing
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• v.18 no.1
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• pp.45-51
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• 2009

Shape memory alloy has been used to improve the tensile strength of composite by the occurrence of compressive residual stress in matrix using its shape memory effect. In order to fabricate shape memory alloy composite, TiNi alloy fiber and Al2024 sheets were used as reinforcing material and matrix, respectively. In this study, TiNi/Al2024 shape memory alloy composite was made by using hot press method. In order to investigate bonding condition between TiNi reinforcement and Al matrix, the micro-structure of interface was observed by using optical microscope and diffusion layer of interface was measured by using Electron Probe Micro Analyser. And the mechanical properties of composite with three parameters(volume fraction of fiber, cold rolling amount and test temperature) were obtained by tensile test. The most optimum bonding condition for fabrication the TiNi/Al2024 composite material was obtained as holding for 30min. under the pressure of 60MPa at 793K. The strength of composite material increased considerably with the volume fraction of fiber up to 7.0%. And the tensile strength of this composite increased with the reduction ratio and it also depends on the volume fraction of fiber.

• Communications for Statistical Applications and Methods
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• v.26 no.5
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• pp.497-506
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• 2019

Forecasting the U.S. employment level is made using machine learning methods of the artificial neural network: deep neural network, long short term memory (LSTM), gated recurrent unit (GRU). We consider the big data of the federal reserve economic data among which 105 important macroeconomic variables chosen by McCracken and Ng (Journal of Business and Economic Statistics, 34, 574-589, 2016) are considered as predictors. We investigate the influence of the two statistical issues of the dimension reduction and time series differencing on the machine learning forecast. An out-of-sample forecast comparison shows that (LSTM, GRU) with differencing performs better than the autoregressive model and the dimension reduction improves long-term forecasts and some short-term forecasts.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2B
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• pp.129-137
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• 2003

Multimedia streams, like MPEG continuously retrieve multimedia data because of their incessant playback. While these streams need an efficient support of kernel, the current buffer cache mechanism of Linux kernel such as Unix operating system was designed apt for small files, which is aperiodically requested as well as time uncritical. But, in case of continuous media, the CPU must enormously copy memory from kernel address space to user address space. This must lead to a large CPU overhead. This overhead both degrades system throughput and cannot guarantee QOS. In this paper, we have designed and implemented two memory copy reduction schemes in Linux kernel, direct I/O and one copy. The direct I/O skips the buffer cache layer of Linux kernel and results in dramatic reduction of CPU memory copy overhead. And, the one copy provides a fast disk-to-network data path without copying to user address space. The experimental results show considerable reduction of CPU overhead and throughput improvements.