• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.26-31
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• 2009

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.69-74
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• 2010

A new package substrate for dynamic random access memory(DRAM) devices has been developed using selective aluminum anodization. Unlike the conventional substrate structure commonly made by laminating epoxy-based core and copper clad, this substrate consists of bottom aluminum, middle anodic aluminum oxide and top copper. Anodization process on the aluminum substrate provides thick aluminum oxide used as a dielectric layer in the package substrate. Placing copper traces on the anodic aluminum oxide layer, the resulting two-layer metal structure is completed in the package substrate. Selective anodization process makes it possible to construct a fully filled via structure. Also, putting vias directly in the bonding pads and the ball pads in the substrate design, via in pad structure is applied in this work. These arrangement of via in pad and two-layer metal structure make routing easier and thus provide more design flexibility. In a substrate design, all signal lines are routed based on the transmission line scheme of finite-width coplanar waveguide or microstrip with a characteristic impedance of about $50{\Omega}$ for better signal transmission. The property and performance of anodic alumina based package substrate such as layer structure, design method, fabrication process and measurement characteristics are investigated in detail.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.4
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• pp.10-15
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• 2012

In a color image, people and especially facial patterns are important and interesting visual objects. Thus, effective skin color reproduction is essential, as skin color is a key memory color in color application systems. Previous studies suggested skin color reproduction by mapping only to the center value of preferred skin region. However, it is not suitable to determine one preference color because preference color from the observer's preference test is not dominant. In this paper, skin color reproduction using multiple preferred skin colors for each race is proposed. The proposed method first defines multiple preferred skin colors for each race according to their luminance level. After that, skin region is detected in an image. The race is then selected by calculating distance between average chromaticity of detected region and that of each racial skin from a database to assign preferred skin color for each race. Next, each corresponding preferred skin color is determined for each selected race. Finally, input skin color is proportionally mapped toward preferred skin color according to the difference between the input skin color and the preferred skin color for a smoothly reproduced skin color. In the experimental results, the proposed method gives better color correction on the objective and subjective evaluation than the previous methods.

• Geophysics and Geophysical Exploration
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• v.7 no.3
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• pp.207-212
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• 2004

This article reviews recent developments in three-dimensional (3-D) magntotelluric (MT) imaging. The inversion of MT data is fundamentally ill-posed, and therefore the resultant solution is non-unique. A regularizing scheme must be involved to reduce the non-uniqueness while retaining certain a priori information in the solution. The standard approach to nonlinear inversion in geophysis has been the Gauss-Newton method, which solves a sequence of linearized inverse problems. When running to convergence, the algorithm minimizes an objective function over the space of models and in the sense produces an optimal solution of the inverse problem. The general usefulness of iterative, linearized inversion algorithms, however is greatly limited in 3-D MT applications by the requirement of computing the Jacobian(partial derivative, sensitivity) matrix of the forward problem. The difficulty may be relaxed using conjugate gradients(CG) methods. A linear CG technique is used to solve each step of Gauss-Newton iterations incompletely, while the method of nonlinear CG is applied directly to the minimization of the objective function. These CG techniques replace computation of jacobian matrix and solution of a large linear system with computations equivalent to only three forward problems per inversion iteration. Consequently, the algorithms are efficient in computational speed and memory requirement, making 3-D inversion feasible.

• Archives of Plastic Surgery
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• v.39 no.5
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• pp.540-545
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• 2012

Background Patients have anxiety and fear of complications due to general anesthesia. Through new instruments and local anesthetic drugs, a variety of anesthetic methods have been introduced. These methods keep hospital costs down and save time for patients. In particular, the target-controlled infusion (TCI) system maintains a relatively accurate level of plasma concentration, so the depth of anesthesia can be adjusted more easily. We conducted this study to examine whether intravenous anesthesia using the TCI system with propofol and remifentanil would be an effective method of anesthesia in breast augmentation. Methods This study recruited 100 patients who underwent breast augmentation surgery from February to August 2011. Intravenous anesthesia was performed with 10 mg/mL propofol and 50 ${\mu}g/mL$ remifentanil simultaneously administered using two separate modules of a continuous computer-assisted TCI system. The average target concentration was set at 2 ${\mu}g/mL$ and 2 ng/mL for propofol and remifentanil, respectively, and titrated against clinical effect and vital signs. Oxygen saturation, electrocardiography, and respiratory status were continuously measured during surgery. Blood pressure was measured at 5-minute intervals. Information collected includes total duration of surgery, dose of drugs administered during surgery, memory about surgery, and side effects. Results Intraoperatively, there was transient hypotension in two cases and hypoxia in three cases. However, there were no serious complications due to anesthesia such as respiratory difficulty, deep vein thrombosis, or malignant hypertension, for which an endotracheal intubation or reversal agent would have been needed. All the patients were discharged on the day of surgery and able to ambulate normally. Conclusions Our results indicate that anesthetic methods, where the TCI of propofol and remifentanil is used, might replace general anesthesia with endotracheal intubation in breast augmentation surgery.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.1-7
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• 2008

Magnetic Tunneling Junction (MTJ) has been used as a nonvolatile universal storage element mainly in memory technology. However, according to several recent studies, magneto-logic using MTJ elements show much potential in substitution for the transistor-based logic device. Magneto-logic based on MTJ can maintain the data during the power-off mode, since an MTJ element can store the result data in itself. Moreover, just by changing input signals, the full logic functions can be realized. Because of its programmability, it can embody the reconfigurable magneto-logic circuit in the rigid physical architecture. In this paper, we propose a novel 3-bit arbitrary magneto-logic circuit beyond the simple combinational logic or the short sequential one. We design the 3-bit magneto-logic which has the most complexity using MTJ elements and verify its functionality. The simulation results are presented with the HSPICE macro-model of MTJ that we have developed in our previous work. This novel magneto-logic based on MTJ can realize the most complex logic function. What is more, 3-bit arbitrary logic operations can be implemented by changing gate signals of the current drivel circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.1-11
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• 2008

This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.