• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.282-291
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• 2010

This paper presents a full-CMOS transmitter and receiver for VDSL2 systems. The transmitter part consists of the low-pass filter, programmable gain amplifier (PGA) and 14-bit DAC. The receiver part consists of the low-pass filter, variable gain amplifier (VGA), and 13-bit ADC. The low pass filter and PGA are designed to support the variable data rate. The RC bank sharing architecture for the low pass filter has reduced the chip size significantly. And, the 80 Msps, high resolution DAC and ADC are integrated to guarantee the SNR. Also, the transmitter and receiver are designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. The chip is implemented in 0.25 ${\mu}m$ CMOS technology and the die area is 5 mm $\times$ 5 mm. The spurious free dynamic range (SFDR) and SNR of the transmitter and receiver are 67.5 dB and 41 dB, respectively. The power consumption of the transmitter and receiver are 160 mW and 250 mW from the supply voltage of 2.5 V, respectively.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1444-1445
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• 2008

최근 Wireless Local Area Network(WLAN), Wide-band Code Division Multiple Access(WCDMA), CDMA2000, Bluetooth 등 다양한 모바일 통신 시스템에 대한 수요가 증가하고 있다. 이와 같은 모바일 통신 시스템에는 70dB이상의 SFDR(Spurious Free Dynamic Range)을 가진 ADC(Analog-to-Digital Converter)가 사용된다. 본 논문에서는 모바일 통신 시스템을 위한 SFDR 70dBc의 성능을 제공하는 10비트, 100Msps 파이프라인 ADC를 제안한다. 제안한 ADC는 요구되는 해상도 및 속도 사양을 만족시키기 위해 3단 파이프라인 구조를 채택하였으며, 입력단 SHA(Sample and Hold)회로에는 Nyquist 입력에서도 10비트 이상의 정확도로 신호를 샘플링하기 위해 부트스트래핑 기법 기반의 샘플링 스위치를 적용하였다. residue amplifier 회로에는 전력을 줄이기 위해 8배 residue amplifier 대신 3개의 2배 ressidue amplifier를 사용하였다. ADC의 높은 사양을 만족시키기 위해서는 높은 이득을 가지는 op-amp가 필수적이다. 제안한 ADC 는 0.18um CMOS 공정으로 설계되었으며, 100Msps의 동작 속도에서 70dBc 수준의 SFDR과 60dB 수준의 SNDR(Signal to Noise and Distortion Ratio)을 보여준다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.684-685
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• 2017

FMCW radar, which is widely used as a front collision warning system for vehicles, is now being commercialized. In this study we develope the radar signal processing system using MPC5775K that is specialized for high performance ADAS. That has special features for ADAS such as 10Msps 12bit ADC, 50MHz Radix-4 FFT, CTE(Cross Triggering Engine) for synchronized triggering between DAC and ADC. The baseband processing board is implemented and shows the result in Matlab.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2100-2106
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• 2007

Multi-stage folding A/D converter circuit with $0.25{\mu}m$ N-well CMOS technology is designed. This A/D converter consists of a transconductance circuit, linear folder circuit and 1bit A/D converter circuit. In H-spice simulation results, linear folder circuits having high linearity can be obtained when the current mode is used instead of voltage mode. And in case of 6bit, the delay time is limited about 40ns. From this results, 6bit 25MSPS A/D converter circuit can be realized.

• Nuclear Engineering and Technology
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• v.56 no.5
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• pp.1836-1844
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• 2024

The use of digital systems in radiation science has been increased last years in the different knowledge areas, as a detectors, spectrometry, spectroscopy, simulation, etc. This manuscript presents the design and implementation of a low-cost, fully portable multi-channel analyzer for nuclear spectrometry (in situ). The development is based on a 32-bit microcontroller with ARM Cortex-M7, this design is able to digitize and analyze pulses from a radiation detector without the need to transform the input signal with some filter, obtains the maximum height of each of the digitized pulses, segmenting the information into channels to form a histogram and visualizing the LCD screen incorporated in the system. A continuous digitization methodology was used, which is in charge of the DMA and an ADC with a resolution of 12 bits at a speed of 3.6 MSPS. The system has a compact design and can open and save spectra in an SD memory built into the system. The MCA in MCU was tested with a NaI(Tl) Scintillation radiation detector, which allowed us to determine that the spectra obtained are similar compared to commercial MCA's. The results obtained show that the MCA in MCU is efficient for nuclear spectrometry, in addition to being very economical and low power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.47-55
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• 2010

In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.

• Journal of the Korea Convergence Society
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• v.8 no.7
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• pp.1-6
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• 2017

This paper presents the design of a frequency measurement device using ADC, EP2AGX FPGA and STM32 processor to accurately measure the frequency of a broadband high frequency signal. The ADC device used in this paper has a sampling frequency of 250 MSPS and a processing frequency bandwidth of 100 MHz. Due to its high sampling frequency, it is difficult to process in ordinary computers or processors, so we implemented the frequency measurement algorithm using the Altra EP2AGX FPGA. The measured frequency is sent to the direction detection controller in real time and fused with the phase signal to calculate the incident azimuth angle of the high frequency signal. The designed frequency measurement device is about 0.2 Mhz in frequency measurement error and 30% less than Anaren DFD-x, which is considered to contribute greatly to the design of radio monitoring and direction detection device.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3A
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• pp.265-271
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• 2009

This paper proposes an efficient initial frequency estimator for Digital Video Broadcasting-Second Generation (DVB-S2). The initial frequency offset of the DVB-S2 is around ${\pm}5MHz$, which corresponds to 20% of the symbol rate at 25Msps. To estimate a large initial frequency offset, the algorithm which call provide a large estimation range is required. Through the analysis of the data-aided (DA) algorithms, we find that the Mengali and Moreli (M&M) algorithm can estimate a large initial frequency offset at low SNR. Since the existing frequency estimator based on M&M algorithm has a high hardware complexity, we propose the methods to reduce the hardware complexity of the initial frequency estimator. This can be achieved by reducing the number of autocorrelators and arctangents. The proposed architecture can reduce the hardware complexity about 64.5% compared to the existing frequency estimator and has been thoroughly verified on the Xilinx Virtex II FPGA board.

• Journal of Navigation and Port Research
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• v.41 no.5
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• pp.277-286
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• 2017

IMO introduced e-Navigation concept to improve the efficiency of ship operation, port operation, and ship navigation technology. IMO proposed sixteen MSPs (Maritime Service Portfolio) applicable to the ships and onshore in case of e-Navigation implementation. In order to meet the demands of the international society, the system implementation work for the Korean e-Navigation has been specified. The Korean e-Navigation system has five service categories: the S2 service category, which is a ship anomaly monitoring service, is a service that classifies emergency levels according to the degree of abnormal condition when a ship has an abnormality in ship operation, and provides guidance for emergency situations. The navigation safety module is a sub-module of the S2 service that determines the emergency level in case of navigation equipment malfunctioning, engine or steering gear failure during navigation. It provides emergency response guidance based on emergency level to the abnormal ship. If an abnormal condition occurs during the ship operation, first, the ship shall determine the emergency level, according to the degree of abnormality of the ship. Second, an emergency response guidance is generated based on the determined emergency level, and the guidance is transmitted to the ship, which helps the navigators prevent accidents and not to spread. In this study, the operational concept for the implementation of the Korean e-Navigation system is designed and the concept is focused on the navigation safety module of S2 service.