• Journal of the Semiconductor & Display Technology
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• v.13 no.3
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• pp.45-50
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• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.163-168
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• 2015

This paper analyzed the deviation of tunneling current for bottom gate voltage of sub-10 nm asymmetric double gate MOSFET. The asymmetric double gate MOSFET among multi gate MOSFET developed to reduce the short channel effects has the advantage to increase the facts to be able to control the channel current, compared with symmetric double gate MOSFET. The increase of off current is, however, inescapable if aymmetric double gate MOSFET has the channel length of sub-10 nm. The influence of tunneling current was investigated in this study as the portion of tunneling current for off current was calculated. The tunneling current was obtained by the WKB(Wentzel-Kramers-Brillouin) approximation and analytical potential distribution derived from Poisson equation. As a results, the tunneling current was greatly influenced by bottom gate voltage in sub-10 nm asymmetric double gate MOSFET. Especially it showed the great deviation for channel length, top and bottom gate oxide thickness, and channel thickness.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.6
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• pp.243-249
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• 2010

In this thesis, in order to a equivalent circuit-analytical study for a symmetric double gate type MOSFET, we slove analytically the 2D Poisson's equation in a a silicon body. To solve the threshold voltage in a symmetric double gate type MOSFET from the derived expression for the surface potential which the two-dimensional potential distribution of a symmetric double gate type MOSFET is assumed approximately. This thesis can use short and long channel in a silicon body we introduce a new the threshold voltage model in a symmetric double gate type MOSFET and measure it the distance about the range of channel length up to 0.1 [${\mu}m$].

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.11
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• pp.62-69
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• 1998

The general degradation model has been applied to analyze the hot carrier induced degradation of the DC and RF characteristics of RF-nMOSFET. The degradation of cut-off frequency has been severer than the degradation of bulk MOSFET drain current. The value of the degradation rate n and the degradation parameter m for RF-nMOSFET has been equal to those for bulk MOSFET. The decrease of device degradation with the increase of fingers could be explained by the large source/drain parasitic resistance and drain saturation voltage. It has been also found that the RF performance degradation could be explained by the decrease of $g_{m}$ and $C_{gd}$ and the increase of $g_{ds}$ after stress. The degradation of the DC and RF characteristics of RF-nMOSFET could be predicted by the measurement of the substrate current.t.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.173-174
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• 2018

This paper compared the electrical coupling of the monolithic 3D inverter consisting of MOSFET and JLFET. In the case of both the MOSFET and the JLFET, MOSFET and JLFET have a small threshold voltage variation when the thickness of inter-layer dielectric (ILD) = 100 nm. However, when the thickness of ILD = 10 nm, the threshold voltage variation is larger and the JLFET is twice as much as the MOSFET.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.161-167
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• 1999

3-input neuron-MOSFET inverters and 3-bit D/A converters using enhancement type device have been designed and fabricated by using standard 2-poly CMOS process. The voltage transfer curve and the noise margin of neuron-MOSFET inverters have been measured and characterized as the same method in normal CMOS inverters. From the theoretical calculation of the effects of coupling ratio on the voltage transfer curve and noise margin, we set up the design guideline for the gate oxide thickness and input gate layout in neuron-MOSFET inverters. BT using one of input gates as a control gate, we can design and fabricate the neuron-MOSFET D/A converter without offset voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.4
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• pp.199-204
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• 2016

This paper was proposed floating island power MOSFET for lowering on state resistance and the proposed device was maintained 600 V breakdown voltage. The electrical field distribution of floating island power MOSFET was dispersed to floating island between P-base and N-drift. Therefore, we designed higher doping concentration of drift region than doping concentration of planar type power MOSFET. And so we obtain the lower on resistance than on resistance of planar type power MOSFET. We needed the higher doping concentration of floating island than doping concentration of drift region and needed width and depth of floating island for formation of floating island region. We obtained the optimal parameters. The depth of floating island was $32{\mu}m$. The doping concentration of floating island was $5{\times}1,012cm^2$. And the width of floating island was $3{\mu}m$. As a result of designing the floating island power MOSFET, we obtained 723 V breakdown voltage and $0.108{\Omega}cm^2$ on resistance. When we compared to planar power MOSFET, the on resistance was lowered 24.5% than its of planar power MOSFET. The proposed device will be used to electrical vehicle and renewable industry.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2655-2661
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• 2009

In this paper, an accurate noise parameters for thermal noise modeling of short channel MOSFET is derived and extracted. Fukui model for calculating the noise parameters of a MOSFET is modified by considering effects of parasitic elements in short channel, and it is compared with conventional noise model equation. In addition, for obtaining the intrinsic noise sources of devices, noise parameters(minimum noise figure $F_{min}$, equivalent noise resistance $R_n$ optimized source admittance $Y_{opt}=G_{opt}+B_{opt}$) in submicron MOSFETs is extracted. With this extraction method, the intrinsic noise parameters of MOSFET without effects of probe pad and extrinsic parasitic elements from RF noise measurements can be directly obtained.

• 전기의세계
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• v.34 no.5
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• pp.292-298
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• 1985

전력 MOSFET은 산업 전반에 걸쳐 수요가 급증하고 있고, 멀지않아 장래에 컴퓨터, 통신, 메카트로닉스, 자동차등의 발달로 인하여 갑작스레 수요가 폭발하리라 예상하고 있다. 전력 MOSFET은 10년도 채 못되는 짧은 역사를 지니고 있기 때문에 국내에는 거의 소개된 바가 없으며, 이를 사용한 시스템을 생산하는 업체도 알려진 바 없다. 그러나, 에너지 자원이 빈곤한 우리나라에서는 전력 MOSFET을 사용한 절전형 전원이나 조절기의 개발이 시급하리라 생각된다. 또한 전력MOSFET은 LSI급의 IC제조시설을 활용하여 제작이 가능하기 때문에, 비교적 소규모 시설 투자에 의해 생산시설을 갖출 수가 있다. 따라서, 국내에서도 반도체 기술의 다양화 측면에서라도 전력MOSFET의 개발을 신중히 검토해야 할 때가 왔다고 생각한다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.10
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• pp.720-725
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• 2013

Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have analyzed trench process, field limit ring process for fabrication of unified trench gate power MOSFET. And we have analyzed electrical characteristics of fabricated unified trench gate power MOSFET. The optimal trench process was based on SF6. After we carried out SEM measurement, we obtained superior trench gate and field limit ring process. And we compared electrical characteristics of planar and trench gate unified power MOSFET after completing device fabrication. As a result, the both of them was obtained 500 V breakdown voltage. However trench gate unified power MOSFET was shown improved Vth and on state voltage drop characteristics than planar gate unified power MOSFET.