• Journal of IKEEE
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• v.25 no.1
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• pp.15-24
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• 2021

In this paper, 1700 V EPDT (Extended P+ shielding floating gate Double Trench) MOSFET structure, which has a smaller switching time and loss than CDT (Conventional Double Trench) MOSFET, is proposed. The proposed EPDT MOSFET structure extended the P+ shielding area of the source trench in the CDT MOSFET structure and divided the gate into N+ and floating P- polysilicon gate. By comparing the two structures through Sentaurus TCAD simulation, the on-resistance was almost unchanged, but Crss (Gate-Drain Capacitance) decreased by 32.54 % and 65.5 %, when 0 V and 7 V was applied to the gate respectively. Therefore, the switching time and loss were reduced by 45 %, 32.6 % respectively, which shows that switching performance was greatly improved.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.442-446
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• 2000

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased parking density. Therefore, it was interested in scaling theory, and full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot carriers in different MOSFET structures. MOSFET structures investigated in this study include a conventional MOSFET with a single source/drain, implant a lightly-doped drain(LDD) MOSFET, and a MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane, and those are analyzed using TCAD(Technology Computer Aided Design) for scaling and simulation. The scaling has used a constant-voltage scaling method, and we have presented MOSFET´s characteristics such as I-V characteristic, impact ionization, electric field and recognized usefulness of TCAD, providing a physical basis for understanding how they relate to scaling.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.226-227
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• 2016

본 논문은 SiC Mosfet Gate Driver에서 Overcurrent상황 발생시 Mosfet 양단의 전압을 검출함으로써 스위칭 소자를 보호하는 Desaturation detction circuit에 대해 다룬다. IGBT와 다르게 SiC Mosfet의 경우 ohmic 영역과 saturation영역의 구분이 명확하지 않기 때문에 과전류 발생시 Mosfet 양단 전압을 검출하는데 어려움이 있다. 따라서 이를 보완하기 위하여 Mosfet drain측에 새로운 회로를 추가로 설계함으로써 이를 보완하여 효과적으로 양단전압을 검출한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.2
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• pp.152-158
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• 1999

Due to high power ratings and low conduction loss, the TGBT has become more attractive in switching power supplies. However, its lower turn-on and turn-off characteristics than those of MOSFET cause severe switching loss and s switching frequency limitation. This paper proposes 2.4kW. 48V. high efficiency half-bridge DC-DC converter using p paralleled TGBT-MOSFET switch concept to use the merits of TGBTs and MOSFETs. Tn parallel switches. each of I TGBT and MOSFET plays its part during on-periods and switching instants. The switching loss is analyzed by l linearized modelling and the operation of the converter are investigated by simulation results.

• Journal of IKEEE
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• v.11 no.3
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• pp.95-99
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• 2007

In this study, the electrical characteristics of Symmetric and Asymmetric High Voltage MOSFET(HV-MOSFET) under high temperature were investigated. And, the specific on-resistance, threshold voltage, transconductance, drain current of the HV-MOSFETs were measured over a temperatures range of 300K ${\leq}$ T ${\leq}$400K. From the result of measured data, specific on-resistance increases slightly with increasing temperature. Especially, at high temperature(at 400K) specific on-resistance was increased about 30% than that in room temperature. And, in high temperature condition (at 400K), drain current was decreased about 30%, Also, transconductance(gm) was decreases with increasing temperature.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.775-777
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• 2016

In this paper presents an analysis of pulsed radiation effects of unit devices. Unit devices are the nMOSFET, pMOSFET, NPN Transistor and those fabricated by the 0.18um CMOS process. Pulsed radiation test results in nMOSFET, the photocurrent of tens nA was generated in $2.07{\times}10^8rad(si)/s$. For the pMOSFET, a photocurrent generation was not observed in $3{\times}10^8rad(si)/s$. For the NPN transistor, the photocurrent was generated with about 1uA. Therefore, the MOSFET must be used than BJT transistor when radhard IC design.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.789-792
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• 2003

pMOSFET having 10 ${\mu}um$ thickness Gd layer has been tested to be used as a slow neutron sensor. The total thermal neutron cross section for the Gd is 47,000 barns and the cross section value drops rapidly with increasing neutron energy. When slow neutrons are incident to the Gd layer, the conversion electrons are emitted by the neutron absorption process. The conversion electrons generate electron-hole pairs in the $SiO_2$ layer of the pMOSFET. The holes are easily trapped in Oxide and act as positive charge centers in the $SiO_2$ layer. Due to the induced positive charges, the threshold turn-on voltage of the pMOSFET is changed. We have found that the voltage change is proportional to the accumulated slow neutron dose, therefore the pMOSFET having a Gd nuclear reaction layer can be used for a slow neutron dosimeter. The Gd-pMOSFET were tested at HANARO neutron beam port and $^{60}CO$ irradiation facility to investigate slow neutron response and gamma response respectively. Also the pMOSFET without Gd layer were tested at same conditions to compare the characteristics to the Gd-pMOSFET. From the result, we have concluded that the Gd-pMOSFET is very sensitive to the slow neutron and can be used as a slow neutron dosimeter. It can also be used in a mixed radiation field by subtracting the voltage change value of a pMOSFET without Gd from the value of the Gd-pMOSFET.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.109-114
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• 2013

Power MOSFET (metal-oxide semiconductor field-effect transistor) are widely used in power electronics applications, such as BLDC (Brushless Direct Current) motor and power module, etc. For the conventional power MOSFET device structure, there exists a tradeoff relationship between specific on-state resistance and breakdown voltage. In order to overcome the tradeoff relationship, a non-uniform super-junction (SJ) trench MOSFET (TMOSFET) structure for an optimal design is proposed in this paper. It is required that the specific on-resistance of non-uniform SJ TMOSFET is less than that of uniform SJ TMOSFET under the same breakdown voltage. The idea with a linearly graded doping profile is proposed to achieve a much better electric field distribution in the drift region. The structure modelling of a unit cell, the characteristic analyses for doping density, and potential distribution are simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the non-uniform SJ TMOSFET shows the better performance than the uniform SJ TMOSFET in the specific on-resistance at the class of 100V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.9-18
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• 2005

To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.

• Journal of IKEEE
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• v.19 no.1
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• pp.94-100
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• 2015

In this paper, 50V power U-MOSFET which replace the body(PN) diode with Schottky is proposed. As already known, Schottky diode has the advantage of reduced reverse recovery loss than PN diode. Thus, the power MOSFET with integrated Schottky integrated can minimize the reverse recovery loss. The proposed Schottky body diode U-MOSFET(SU-MOS) shows reduction of reverse recovery loss with the same transfer, output characteristic and breakdown voltage. As a result, 21.09% reduction in peak reverse current, 7.68% reduction in reverse recovery time and 35% improvement in figure of merit(FOM) are observed when the Schottky width is $0.2{\mu}m$ and the Schottky barrier height is 0.8eV compared to conventional U-MOSFET(CU-MOS). The device characteristics are analyzed through the Synopsys Sentaurus TCAD tool.