• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.8
• /
• pp.1010-1018
• /
• 1988

This paper proposes a MOS circuit extractor which extracts a netlist from the hierarchical mask information, for the verification tools. To utilize the regularity and the simple representation of the hierarchical circuit, and to reduce the debug cycle of design, verification, and modification, we propose a hierarvhical and incremental circuit extraction algorithm. In flat circuit extraction stage, the multiple storage quad tree is used as an internal data structure. Incremental circuit extraction using the hierarchical structure is made possible, to reduce the re-extraction time of the modified circuit.

• Journal of IKEEE
• /
• v.12 no.4
• /
• pp.211-216
• /
• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the KIEE Conference
• /
• 1986.07a
• /
• pp.417-421
• /
• 1986

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.105-106
• /
• 2005

The impact ionization MOS (I-MOS) transistor with 50nm channel length is presented by using 2-D device simulator ISE-TCAD. The subthreshold slope cannot be steeper than kT/q since the subthreshold conduction is due to diffusion current. As MOSFETs are scaled down, this problem becomes significant and the subthreshold slope degrades which leads an increase in the off-current and off-state power dissipation. The I-MOS is based on a gated p-i-n structure and the subthreshold conduction is induced by impact ionization. The simulation results show that the subthreshold slope is 11.7 mV/dec and this indicates the I-MOS improves the switching speed and off-state characteristics.

• Proceedings of the KIEE Conference
• /
• 1984.07a
• /
• pp.205-206
• /
• 1984

• Proceedings of the KIEE Conference
• /
• 1985.07a
• /
• pp.185-186
• /
• 1985

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1992.11a
• /
• pp.123-127
• /
• 1992

When MOS devices is exposed to radiation, radiation effects of P-type MOS capacitor can cause modulation and/or degradation in devices characteristics and its operating life. The oxide layer is grown in $O_2$+T.C.E. and its thickness ranges from 40 to 80 nm. Irradiations on MOS capacitor were performed by Cobalt-60 gamma ray source and total dose ranges from $10^4$ to $10^8$ rads. The radiation effect on electrical conduction characteristics(I-V) in MOS capacitor was measured as a function of gate oxide thickness and total dose. From the experimental result, I-V characteristics is found to be influenced strongly by total dose in irradiated p-type MOS capacitors. The ohmic current is dependant on of total dose in irradiated P-type MOS capacitors. This results are explained using surface states at interface radiation-induced traps.

• Journal of the military operations research society of Korea
• /
• v.25 no.1
• /
• pp.142-159
• /
• 1999

To assign the soldiers in the adequate positions I military is almost as important as managing officers because they compose the main part of military structure and equipment operators. The current Military Occupational Specialty(MOS) assignment system lacks the capability to optimize the use of recruit's potential. We suggest an MOS assignment method for enlisted recruits using the Analytic Hierarchy Process(AHP) method, this method systematically provides a method of calculation of composite relative weights of decision elements to be considered during MOS assignment and a method of quantification for personal quality of new recruits. The quantified value of personal quality, Mission Performance Capability(MPC), in this study means the mission performance capability when a personnel is assigned to a certain MOS. This paper develops a multiple objectives MOS assignment model for enlisted recruits. It uses MPC of personnels, calculated with AHP method and consensus method, as parameters. The goal constraints are assurance of filling requirement, minimization of the number of unassigned personnel to MOS, capability satisfaction of education facility and support facility, assurance of desired MPC value level for MOS assignment, and maximization of total MPC. The objective function is to terminalization of the negative or positive deviation for the above goal constraints.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.1
• /
• pp.41-44
• /
• 2004

The trend of decreasing the minimal structure sizes in microelectronics is still being continued. Therefore in its roadmap the Semiconductor Industries Association predicts a printed minimum MOS-transistor channel length of 10 nm for the year 2018. Although the resolution of optical lithography still dramatically increases, there are known and proved solutions for structure sizes significantly below 50 nm up to now. In this work a new method for the fabrication of extremely small MOS-transistors with a channel length and width below 50 nm with low demands to the used lithography will be explained. It's a further development of our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, with a scaling of the transistor's width. The used technique is proved in a first charge of MOS-transistors with a channel area of W=200 nm and L=80 nm. The full CMOS compatible technique is easily transferable to almost any other technology line and results in an excellent homogeneity and reproducibility of the generated structure size. The electrical characteristics of such small transistor will be analyzed and the ultimate limits of the technique will be discussed.

• The KIPS Transactions:PartA
• /
• v.17A no.3
• /
• pp.121-126
• /
• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.