• Title/Summary/Keyword: MOS device

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Electrical Characteristics of Thin SiO$_2$Layer

  • Hong, Nung-Pyo;Hong, Jin-Woong
    • KIEE International Transactions on Electrophysics and Applications
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    • v.3C no.2
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    • pp.55-58
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    • 2003
  • This paper examines the electrical characteristic of single oxide layer due to various diffusion conditions, substrate orientations, substrate resistivity and gas atmosphere in a diffusion furnace. The oxide quality was examined through the capacitance-voltage characteristic due to the annealing time after oxidation process, and the capacitance-voltage characteristics of the single oxide layer by will be described via semiconductor device simulation.

New NH-O Oxidation method (II)-For the Electrical properties of Device. (새로운 $NH_{3}-O_{2}$ 산화 방법(II)-소자의 전기적 특성)

  • Jeong, Seong-An;Park, Sun-Woo;Kim, Chul-Ju
    • Proceedings of the KIEE Conference
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    • 1988.07a
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    • pp.363-366
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    • 1988
  • A new $NH_{3}-O_{2}$ oxidation method was estimated by the electrical properties of the fabricated n-MOS transistor. For the C-V characteristic curves the Qox are almost equal to Qss and no hysteresis phenomena are observed. The Id-Vds characteristics show that $NH_{3}-O_{2}$ oxidation method is superior to Dry oxidation.

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The Effect of the Microdefects in Czoscralski Si wafer on Thin Oxide Failures (Thin Oxide 불량에 미치는 Czochralski Si 웨이퍼의 미소결함의 영향)

  • 박진성;이우선;김갑식;문종하;이은구
    • Journal of the Korean Ceramic Society
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    • v.34 no.7
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    • pp.699-702
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    • 1997
  • The cross sectional image of thin oxide failure of MOS device could be observed by Emission Microscope and Focused Ion Beam at the weak point. The oxide failures in low electric field was associated with the presence of a particle or abnormal pattern. The failures occuring at medium field are related to a pit of Si substrate. The pits could be originated from the microdefects of Cz Si wafer.

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Reducing the Poly-Si TFT Non-Uniformity by Transistor Slicing

  • Lee, Min-Ho;Lee, In-Hwan
    • Journal of Information Display
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    • v.2 no.2
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    • pp.27-31
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    • 2001
  • Transistor slicing refers to the use of multiple smaller transistors in implementing a large MOS transistor. What is special about transistor slicing is that it can reduce the effects of device non-uniformity introduced during the fabrication process. The paper presents the idea of transistor slicing and analyzes the benefits of using transistor slicing in the context of Poly-Si TFT-LCD driving.

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Effects of Vth adjustment ion implantation on Switching Characteristics of MCT(MOS Controlled Thyristor) (문턱전압 조절 이온주입에 따른 MCT (MOS Controlled Thyristor)의 스위칭 특성 연구)

  • Park, Kun-Sik;Cho, Doohyung;Won, Jong-Il;Kwak, Changsub
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.5
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    • pp.69-76
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    • 2016
  • Current driving capability of MCT (MOS Controlled Thyristor) is determined by turn-off capability of conducting current, that is off-FET performance of MCT. On the other hand, having a good turn-on characteristics, including high peak anode current ($I_{peak}$) and rate of change of current (di/dt), is essential for pulsed power system which is one of major application field of MCTs. To satisfy above two requirements, careful control of on/off-FET performance is required. However, triple diffusion and several oxidation processes change surface doping profile and make it hard to control threshold voltage ($V_{th}$) of on/off-FET. In this paper, we have demonstrated the effect of $V_{th}$ adjustment ion implantation on the performance of MCT. The fabricated MCTs (active area = $0.465mm^2$) show forward voltage drop ($V_F$) of 1.25 V at $100A/cm^2$ and Ipeak of 290 A and di/dt of $5.8kA/{\mu}s$ at $V_A=800V$. While these characteristics are unaltered by $V_{th}$ adjustment ion implantation, the turn-off gate voltage is reduced from -3.5 V to -1.6 V for conducting current of $100A/cm^2$ when the $V_{th}$ adjustment ion implantation is carried out. This demonstrates that the current driving capability is enhanced without degradation of forward conduction and turn-on switching characteristics.

Design of a DC-DC Converter for Portable Device (휴대기기용 DC-DC 부스트 컨버터 집적회로설계)

  • Lee, Ja-kyeong;Song, Han-Jung
    • Journal of Korea Society of Industrial Information Systems
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    • v.22 no.2
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    • pp.71-78
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    • 2017
  • In This Paper, A DC-DC Boost Converter for Portable Device has been Proposed. The Converter Which is Operated with 1 MHz High Switching Frequency is Capable of Reducing Mounting Area of Passive Devices Such as Inductor and Capacitor, Consequently is Suitable for Portable Device. This Boost Converter Consists of a Power Stage and a Control Block and a Protect Block. Proposed DC-DC Boost Converter has been Designed a 0.18 um Magnachip CMOS Process Technology, we Examined Performances of the Fabricated Chip and Compared its Measured Results with SPICE Simulation Data. Simulation Results Show that the Output Voltage is 4.8 V in 3.3 V Input Voltage, Output Current 95 mA Which is Larger than 20~50 mA.

Reconstruction of Transmitted Frames for Visual Quality Assessment of Streaming Video (스트리밍 비디오 화질 평가를 위한 수신 영상 복원)

  • Park, Su-Kyung;Sim, Dong-Gyu
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.46 no.1
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    • pp.32-40
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    • 2009
  • In this paper, we proposed an reconstruction algorithm of transmitted frames from displayed image on video terminal. For image quality assessment of the video streaming in the wireless network, we need information of the image that is transmitted to the end-user's device. Generally, subjective methods are widely used to evaluate the image quality by human beings because it is difficult to extract the transmitted image from the end-user's device. This paper presents an image reconstruction algerian based on the displayed image in video terminal for the extraction of the transmitted image. In the proposed method, we acquired the displayed image on video terminal using the camera. Camera-acquired images exhibit geometric and color distortions caused by characteristics of cameras and display devices. Therefore we correct the geometric distortion by exploiting the homography and color distortion by pre-computed look-up table. The experimental results show that the proposed measurement system yields promising estimation performance in terms of PSNR of $27{\sim}28dB$. We also carried out performance evaluation of the proposed method in terms of EPSNR and the quality of the estimated images by the proposed algerian was in fairly good range of MOS test scale.

Modeling for Memristor and Design of Content Addressable Memory Using Memristor (멤리스터의 모델링과 연상메모리(M_CAM) 회로 설계)

  • Kang, Soon-Ku;Kim, Doo-Hwan;Lee, Sang-Jin;Cho, Kyoung-Rok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.7
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    • pp.1-9
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    • 2011
  • Memristor is a portmanteau of "memory resistor". The resistance of memristor is changed depends on the history of electric charge that passed through the device and it is able to memorize the last resistance after turning off the power supply. This paper presents this device that has a high chance to be the next generation of commercial non-volatile memory and its behavior modeling using SPICE simulation. The memristor MOS content addressable memory (M_CAM) is also designed and simulated using the proposed behavioral model. The proposed M_CAM unit cell area and power consumption show an improvement around 40% and 96%, respectively, compare to the conventional SRAM based CAMs. The M_CAM layout is also implemented using 0.13${\mu}m$ mixed-signal CMOS process under 1.2 V supply voltage.

The characteristics of source/drain structure for MOS typed device using Schottky barrier junction (Schottky 장벽 접합을 이용한 MOS형 소자의 소오스/드레인 구조의 특성)

  • 유장열
    • Journal of the Korean Institute of Telematics and Electronics T
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    • v.35T no.1
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    • pp.7-13
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    • 1998
  • The VLSI devices of submicron level trend to have a lowering of reliability because of hot carriers by two dimensional influences which are caused by short channel effects and which are not generated in a long channel devices. In order to minimize the two dimensional influences, much research has been made into various types of source/drain structures. MOS typed tunnel transistor with Schottky barrier junctions at source/drain, which has the advantages in fabrication process, downsizing and response speed, has been proposed. The experimental device was fabricated with p type silicon, and manifested the transistor action, showing the unsaturated output characteristics and the high transconductance comparing with that in field effect mode. The results of trial indicate for better performance as follows; high doped channel layer to lower the driving voltage, high resistivity substrate to reduce the leakage current from the substrate to drain.

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A New Method for Extracting Interface Trap Density in Short-Channel MOSFETs from Substrate-Bias-Dependent Subthreshold Slopes

  • Lyu, Jong-Son
    • ETRI Journal
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    • v.15 no.2
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    • pp.11-25
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    • 1993
  • Interface trap densities at gate oxide/silicon substrate ($SiO_2/Si$) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.

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