Modeling for Memristor and Design of Content Addressable Memory Using Memristor

멤리스터의 모델링과 연상메모리(M_CAM) 회로 설계

  • Kang, Soon-Ku (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University) ;
  • Kim, Doo-Hwan (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University) ;
  • Lee, Sang-Jin (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University) ;
  • Cho, Kyoung-Rok (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University)
  • 강순구 (충북대학교 정보통신공학과) ;
  • 김두환 (충북대학교 정보통신공학과) ;
  • 이상진 (충북대학교 정보통신공학과) ;
  • 조경록 (충북대학교 정보통신공학과)
  • Received : 2010.09.27
  • Accepted : 2011.07.03
  • Published : 2011.07.25

Abstract

Memristor is a portmanteau of "memory resistor". The resistance of memristor is changed depends on the history of electric charge that passed through the device and it is able to memorize the last resistance after turning off the power supply. This paper presents this device that has a high chance to be the next generation of commercial non-volatile memory and its behavior modeling using SPICE simulation. The memristor MOS content addressable memory (M_CAM) is also designed and simulated using the proposed behavioral model. The proposed M_CAM unit cell area and power consumption show an improvement around 40% and 96%, respectively, compare to the conventional SRAM based CAMs. The M_CAM layout is also implemented using 0.13${\mu}m$ mixed-signal CMOS process under 1.2 V supply voltage.

멤리스터(Memristor)는 메모리 레지스터의 합성어로 흐른 전하량에 따라 저항이 스스로 변하고 전원이 끊긴 상태에서도 저항 상태가 기억되는 특수한 메모리 소자이다. 본 논문에서는 차세대 메모리소자로 주목받고 있는 멤리스터를 모델링하고 SPICE 시뮬레이션을 위한 behavior모델을 제시한다. 그리고 제안된 모델을 바탕으로 멤리스터 기반의 M_CAM(Memristor MOS content addressable memory)을 설계하였다. 제안된 M_CAM은 기존의 CAM에 비해서 단위 셀 면적과 평균 전력소모가 각각 40%, 96% 감소하였다. 칩은 0.13${\mu}m$ CMOS 공정에서 공급전압이 1.2V를 갖도록 설계되었다.

Keywords

References

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