• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.76-82
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• 2003

The robust stack storage node and sufficient cell capacitance for high performance is indispensable for 90 nm DRAM capacitor. For the first time, we successfully demonstrated MIS capacitor process integration for 90 nm DRAM technology. Novel cell layout and integration technology of 90 nm DRAM capacitor is proposed and developed, and it can be extended to the next generation DRAM. Diamond-shaped OCS with 1.8 um stack height is newly developed for large capacitor area with better stability. Furthermore, the novel $Al_2O_3/HfO_2$ dielectric material with equivalent oxide thickness (EOT) of 25 ${\AA}$ is adopted for obtaining sufficient cell capacitance. The reliable cell capacitance and leakage current of MIS capacitor is obtained with ~26 fF/cell and < 1 fA/ceil by $Al_2O_3/HfO_2$ dielectric material, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.13-14
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• 2008

$Al_2O_3$ thin films were deposited on GaN (0001) by remote plasma atomic layer deposition (RPALD) technique using trimethylaluminum (TMA) precursor and oxygen radicals in the temperature range of 25 ~ $500^{\circ}C$. Growth rate per cycle was varied with substrate temperature from 1.8 $\breve{A}$/ cycle at $25^{\circ}C$ to 0.8 $\breve{A}$/cycle at $500^{\circ}C$. The chemical structure of the $Al_2O_3$ thin films was studied using X-ray photo electron spectroscopy (XPS). Excellent electrical properties of $Al_2O_3$/GaN MIS capacitor were grown at $300^{\circ}C$ process temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.29-32
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• 1999

$GaF_3$ films were directly grown on p' and p-type GaAs(100) substrates using a $SF_6$ plasma discharge system. GaAs MIS(Meta1-Insulator-Semiconductor) capacitor was successfully fabricated for about 1 hour at temperature $290^{\circ}C$ using the as-grown $GaF_3$ films. The as-grown films on p'-GaAs exhibited a current density of less than 6.68 $\times$ $1O^{-9}$ A/$cm^2$ at a breakdown field of 500kV/cm and a refractive index of 2.0 ~ 2.3 at a wavelength of 632.8 nm. The dielectric constant was about 5 derived from 1 MHz capacitance-voltage (C-V) measurements. Dielectric dispersion of the fluoridated films on p'-GaAs measured ranged from 100 Hz to 10 MHz was not observed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.800-803
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• 2002

The MONOS capacitor are fabricated to investigate the carrier trapping due to Fowler-Nordheim tunneling injection. The carrier trapping in scaled multi-dielectric(ONO) depends on the nitride and Op oxide thickness under Fowler_Nordheim tunneling injection. Carriers captured at nitride film could not escape from nitride to gate, but be captured at top oxide and nitride interface traps because of barrier height of top oxide. Therefore, it is expected that the MONOS memory devices using multi dielectric films enhance memory effect and have a long memory retention characteristic.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1919-1921
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• 1999

AlN thin films were fabricated by sputter for the application of MIS device with Al/AlN/Si structure. We controled that sub-temperature room-temperature. Sputtering pressure 5 mTorr, flow ratio Ar:$N_2$=1:1(4sccm:4sccm), and appended hydrogen gas $0{\sim}5%$. AlN thin films thickness fabricated to maintain $2700{\AA}$ time control. Before the experiment remove to the contaminated material use the Ultrasonic every 10 minute use the acetone and ethanol, then use the HF remove oxide-substance at 10 second. To analyze characteristic of the $H_2$ gas addition period, C-V and I-V characteristic make and experiment $H_2$ gas at addition period progressive capability of I-V and C-V characteristic.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.551-552
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• 2006

Plasma-induced charging damage was been measured during TaN gate electrode of MISFET(TaN/$HfO_2$/Si) or interconnection metal etching step using large antenna structures. The results of these experiments were obtained that $HfO_2$ gate dielectric layer was affected about plasma charging effects and damage increased with F-N tunneling. Therefore, the etching conditions should be optimized to avoid the defects caused by plasma charging.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.155-158
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• 1998

MLS capacitor with lipid ultra thin films were deposited by Langmuir-Blodgett (LB) method on the sillicon wafer. The current versus voltage and capacitance versus voltage relationships are depend on the applied voltage, electrode area and electrode materials. LB films deposited were made of L-$\alpha$-DLPC, the 1 layer's thickness of 35$\AA$ was measured by ellipsometer. And MLS capacitor with different electrode materials, the work function of these materials was investigated to increase the leakage current. The result indicated the lower leakage current and very high saturation value of capacitance was reached within 700-800 pF when the two electrode was Ag. And $\varepsilon$$_1$, $\varepsilon$$_2$ versus photon energy showed good film formation.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1925-1927
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• 1999

At the study, it has fabricated Al/AlN/GaAs MIS capacitor using DC reactive sputtering method. To applicate GaAs semiconductor in a MIS devices, investigated capability of AIN thin film by the insulator layer. Also it has investigated inversion of C-V characteristics by addition of the hydrogen(hydrogen concentration: 5%) and it has investigated that leakage current has $10^{-8}A/cm^2$ for 1 MV/cm breakdown electric field of I-V characteristics.

• Korean Journal of Materials Research
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• v.27 no.1
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• pp.48-52
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• 2017

In this study, we used I-V spectroscopy, photoconductivity (PC) yield and internal photoemission (IPE) yield using IPE spectroscopy to characterize the Schottky barrier heights (SBH) at insulator-semiconductor interfaces of Pt/$HfO_2$/p-type Si metal-insulator-semiconductor (MIS) capacitors. The leakage current characteristics of the MIS capacitor were analyzed according to the J-V and C-V curves. The leakage current behavior of the capacitors, which depends on the applied electric field, can be described using the Poole-Frenkel (P-F) emission, trap assisted tunneling (TAT), and direct tunneling (DT) models. The leakage current transport mechanism is controlled by the trap level energy depth of $HfO_2$. In order to further study the SBH and the electronic tunneling mechanism, the internal photoemission (IPE) yield was measured and analyzed. We obtained the SBH values of the Pt/$HfO_2$/p-type Si for use in Fowler plots in the square and cubic root IPE yield spectra curves. At the Pt/$HfO_2$/p-type Si interface, the SBH difference, which depends on the electrical potential, is related to (1) the work function (WF) difference and between the Pt and p-type Si and (2) the sub-gap defect state features (density and energy) in the given dielectric.