• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.993-994
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• 2008

Electrochromic (EC) devices are capable of reversibly changing their optical properties upon charge injection and extraction induced by the external voltage. The characteristics of the EC device, such as low power consumption, high coloration efficiency, and memory effects under open circuit status, make them suitable for use in a variety of applications including smart windows and electronic papers. Coloration due to reduction or oxidation of redox chromophores can be used for EC devices (e-paper), but the switching time is slow (second level). Recently, with increasing demand for the low cost, lightweight flat panel display with paper-like readability (electronic paper), an EC display technology based on dye-modified $TiO_2$ nanoparticle electrode was developed. A well known organic dye molecule, viologen, was adsorbed on the surface of a mesoporous $TiO_2$ nanoparticle film to form the EC electrode. On the other hand, ZnO is a wide bandgap II-VI semiconductor which has been applied in many fields such as UV lasers, field effect transistors and transparent conductors. The bandgap of the bulk ZnO is about 3.37 eV, which is close to that of the $TiO_2$ (3.4 eV). As a traditional transparent conductor, ZnO has excellent electron transport properties, even in ZnO nanoparticle films. In the past few years, one-dimension (1D) nanostructures of ZnO have attracted extensive research interest. In particular, 1D ZnO nanowires renders much better electron transportation capability by providing a direct conduction path for electron transport and greatly reducing the number of grain boundaries. These unique advantages make ZnO nanowires a promising matrix electrode for EC dye molecule loading. ZnO nanowires grow vertically from the substrate and form a dense array (Fig. 1). The ZnO nanowires show regular hexagonal cross section and the average diameter of the ZnO nanowires is about 100 nm. The cross-section image of the ZnO nanowires array (Fig. 1) indicates that the length of the ZnO nanowires is about $6\;{\mu}m$. From one on/off cycle of the ZnO EC cell (Fig. 2). We can see that, the switching time of a ZnO nanowire electrode EC cell with an active area of $1\;{\times}\;1\;cm^2$ is 170 ms and 142 ms for coloration and bleaching, respectively. The coloration and bleaching time is faster compared to the $TiO_2$ mesoporous EC devices with both coloration and bleaching time of about 250 ms for a device with an active area of $2.5\;cm^2$. With further optimization, it is possible that the response time can reach ten(s) of millisecond, i.e. capable of displaying video. Fig. 3 shows a prototype with two different transmittance states. It can be seen that good contrast was obtained. The retention was at least a few hours for these prototypes. Being an oxide, ZnO is oxidation resistant, i.e. it is more durable for field emission cathode. ZnO nanotetropods were also applied to realize the first prototype triode field emission device, making use of scattered surface-conduction electrons for field emission (Fig. 4). The device has a high efficiency (field emitted electron to total electron ratio) of about 60%. With this high efficiency, we were able to fabricate some prototype displays (Fig. 5 showing some alphanumerical symbols). ZnO tetrapods have four legs, which guarantees that there is one leg always pointing upward, even using screen printing method to fabricate the cathode.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.109-117
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• 2004

In this paper, a K-band local oscillator composed of a VCDRO(Voltage Controlled Dielectric Resonator Oscillator), GaAs MESFET, and Reflector type frequency doubler has been designed and fabricated. TO obtain a good phase noise performance of a VCDRO, a active device was selected with a low noise figure and a low flicker noise MESFET and a dielectric resonator was used for selecting stable and high oscillation frequency. Especially, to have a higher conversion gain than a conventional doubler as well as a good harmonic suppression performance with circuit size reduced a doubler structure was employed as the Reflector type composed of a reflector and a open stub of quarter wave length for rejecting the unwanted harmonics. The measured results of fabricated oscillator show that the output power was 5.8 dBm at center frequency 12.05 GHz and harmonic suppression -37.98 dBc, Phase noise -114 dBc at 100 KHz offset frequency, respectively, and measured results show of fabricated frequency doubler, the output power at 5.8 dBm of input power is 1.755 dBm conversion gain 1.482 dB, harmonic suppression -33.09 dBc, phase noise -98.23 dBc at 100 KHz offset frequency, respectively. This oscillator could be available to a local oscillator in K-band which used frequency doubler techniques.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.57-63
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• 2014

This paper proposes an architecture of $3^{rd}$ order SDM(Sigma-Delta Modulator) with delayed feed-forward path in order to reduce the power consumption and area. The proposed SDM improve the architecture of conventional $3^{rd}$ order SDM which consists of two integrators. The proposed architecture can increase the coefficient values of first stage doubly by inserting the delayed feed-forward path. Accordingly, compared with the conventional architecture, the capacitor value($C_I$) of first integrator is reduced by half. Thus, because the load capacitance of first integrator became the half of original value, the output current of first op-amp is reduced as 51% and the capacitance area of first integrator is reduced as 48%. Therefore, the proposed method can optimize the power and the area. The proposed architecture in this paper is simulated under conditions which are supply voltage of 1.8V, input signal 1Vpp/1KHz, signal bandwidth of 24KHz and sampling frequency of 2.8224MHz in the 0.18um CMOS process. The simulation results are SNR(Signal to Noise Ratio) of 88.9dB and ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the proposed SDM is $180{\mu}W$.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.1-7
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• 2006

3-dimensional(3-D) simulations of ideal double-gate bulk FinFET were performed extensively and the electrical characteristics. were analyzed. In 3-D device simulation, we changed gate length($L_g$), height($H_g$), and channel doping concentration($N_b$) to see the behaviors of the threshold voltage($V_{th}$), DIBL(drain induced barrier lowering), and SS(subthreshold swing) with source/drain junction depth($X_{jSDE}$). When the $H_g$ is changed from 30 nm to 45nm, the variation gives a little change in $V_{th}$(less than 20 mV). The DIBL and SS were degraded rapidly as the $X_{jSDE}$ is deeper than $H_g$ at low fin body doping($1{\times}10^{16}cm^{-3}{\sim}1{\times}10^{17}cm^{-3}$). By adopting local doping at ${\sim}10nm$ under the $H_g$, the degradation could be suppressed significantly. The local doping also alleviated $V_{th}$ lowering by the shallower $X_{jSDE}\;than\;H_g$ at low fin body doping.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.750-755
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• 2003

This paper proposes a new three-line balun. The equivalent circuit of the proposed three-line balun is presented, and impedance matrix［Z］of the equivalent circuit is derived from the relationship between the current and voltage at each port. The design equation for a given set of balun impedance at input and output ports is presented using［S］parameters, which is transferred fom impedance matrix,［Z］. To demonstrate the feasibility and validity of design equation, multi-layer ceramic(MLC) chip balun operated in the 2.4 GHz ISM band frequency is designed and fabricated by the use of the low temperature co-fired ceramic(LTCC) technology. By employing both the proposed new three-line balun equivalent circuit and multi-layer configuration provided by LTCC technology, the 2012 size MLC balun is realized. Measured results of the multi-layer LTCC three-line balun match well with the full-wave electromagnetic simulation results, and measured in band-phase and amplitude balances over a wide bandwidth are excellent. This proposed balun is very easily applicable to multi-layer structure using LTCC as shown in the paper, and also can be realized with microstrip lines on PCB. This distinctive performance is very favorable for wireless communication systems such as wireless LAN(Local Area Network) and Bluetooth applications.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.10
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• pp.629-636
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• 2016

This study presents the development of an acid resistance velocity sensor that is used for measuring velocity inside a copper sulfate plating bath. First, researchers investigated the acid resistance coating to confirm the suitability of the anti-acid sensor in a very corrosive environment. Then, researchers applied signal processing methods to reduce noise and amplify the signal. Next, researchers applied a pressure-resistive sensor with an operation amplifier (Op Amp) and low-pass filter with high impedance to match the output voltage of a commercial flowmeter. Lastly, this study compared three low-pass filters (Bessel, Butterworth and Chebyshev) to select the appropriate signal process circuit. The results show 0.0128, 0.0023, and 5.06％ of the mean square error, respectively. The Butterworth filter yielded more precise results when compared to a commercial flowmeter. The acid resistive sensor is capable of measuring velocities ranging from 2 to 6 m/s with a 2.7％ margin of error.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.41 no.10
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• pp.788-795
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• 2013

A magnesium bipolar plate whose surface was protected by thinly deposited silver layer was investigated as an alternative to existing graphite bipolar plate of PEM fuel cells. Thin silver layer of $3{\mu}m$ was deposited on a magnesium alloy substrate by physical vapor deposition (PVD) method in an environment of $180^{\circ}C$. A number of tests were conducted on the fabricated magnesium based bipolar plates to determine their suitability for use in PEM fuel cell stacks. The test on corrosion resistance in the same pH condition as in a PEM operation demonstrated the layer protected the magnesium alloy substrate, while unprotected substrate suffered from severe corrosion. The contact resistance of the fabricated bipolar plate was less than $20m{\Omega}-cm^2$ which was superior to the conventional bipolar plates. A single cell was constructed using the fabricated bipolar plates and power output was measured. Due to the enhanced conductivity caused by low contact resistance, slight increase was observed in current density and output voltage. With low density of the magnesium substrate and ease on machining, the weight reduction of the stack of 30~40 % is possible to produce the same power output.