• The Korean Journal of Nuclear Medicine
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• v.30 no.1
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• pp.130-138
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• 1996

Bone scan is known to be an effective tool for observing the state of soft tissues and bones of electric burn patients. It is also used for observing the progress of patients after debridement or skin graft as well as deforming to amputate specific body parts. To evaluate bone scan's role in electric burn, we analyzed bone scan 37 patients with electric burn. Among the 37 patients, 8 of 37 were injured in low voltage and 29 of them in high voltage. 27 patients received the electrical input through the hand, 6 through the scalp, 2 through the shoulder, 1 through the left chest wall and 1 through the left inguinal area. Among 29 patients received high voltage, 22 patients had the electrical output through the foot, 3 through the hand, 2 through the shoulder, 1 through the buttock and 1 through the left chest wall. Bone scans revealed cellulitis in 37 patients with 47 sites, osteomyelitis in 15 patients with 15 sites & bone defects in 4 patients with 4 sites. In 4 patients with skin graft or skin flap, follow up bone scan showed improvements of bony uptake in preoperatively bony defect area and all of them were healed without complication. There were 2 cases in which uptake increased in the myocardium, 1 in the liver and 6 in the kidney, however, serum calcium level, EKG, cardiac enzyme, liver and renal function tests were normal. In conclusion, bone scans are helpful in the assessment of injury sites after electrical insult and in differential diagnosis of cellulitis and osteomyelitis. It is also useful tool of assessment after skin graft or skin flap, however, it should be further evaluated about internal organ damage.

• Journal of the Korean Society of Radiology
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• v.10 no.2
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• pp.109-115
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• 2016

Despite of increasing the use of the digital imaging device in the radiology area, the setting on the optimal irradiation conditions are insufficient. In this study, the exposure dose and image quality by exposure condition of digital radiography device were compared. The exposure doses were obtained by adjusting the exposure condition as 5 steps respectively based on the exposure conditions that are currently used of CR and DR radiography devices. The acquired image has been assessed by 20 medical image professors using the assessment method of the Japanese Society for Tuberculosis Prevent. As a result, in the case of the CR system, the better image quality was obtained in the condition of 120 kVp and 1.5 mAs~2.4 mAs (quality score 91~95.5 points) than standard exposure condition(110 kVp, 3.2 mAs, 86 points). And exposure dose was evaluated as low with $61.3{\sim}98.4{\mu}Gy$ than standard condition($105.11{\mu}Gy$). In DR system, however, the image quality score was higher as 97~98.6 points in the lower tube voltage range (112 kVp, 2.4~3.2 mAs) condition than the standard exposure condition (125 kVp, 3.2 mAs, 91 points). In addition, the exposure dose was $61.5-77.2{\mu}Gy$ lower than standard condition($93{\mu}Gy$). In addition, the exposure dose was low as $61.5-77.2{\mu}Gy$ than standard condition($93{\mu}Gy$). With the results of this study, we confirmed that it is possible to reduce the patient exposure dose with the same image quality by adjusting the optimal exposure condition of digital device.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Korean Society of Radiology
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• v.17 no.3
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• pp.305-314
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• 2023

With the development of medical technology and radiation treatment equipment, the frequency of high-precision radiation therapy such as intensity modulation radiation therapy has increased. Image-guided radiation therapy has become essential for radiation therapy in precise and complex treatment plans. In particular, with the introduction of imaging equipment for diagnosis in a linear accelerator, CBCT scanning became possible, which made it possible to calibrate and correct the patient's posture through 3D images. Although more precise reproduction of the patient's posture has become possible, the exposure dose delivered to the patient during the image acquisition process cannot be ignored. Radiation optimization is necessary in the field of radiation therapy, and efforts to reduce exposure are necessary. However, when acquiring 3D CBCT images by changing the imaging conditions to reduce exposure, there should be no image quality or artefacts that would make it impossible to align the patient's position. In this study, Rando phantom was used to scan and evaluate images for each shooting condition. The highest SNR was obtained at 100 kV 80 mA 25 ms F1 filter 180°. As the tube voltage and tube current increased, the noise decreased, and the bowtie filter showed the optimal effect at high tube current. Based on the actual scanned images, it was confirmed that patient alignment was possible under all imaging conditions, and that image-guided radiation therapy for patient alignment was possible under the condition of 70 kV 10 mA 20 ms F0 filter 180°, which showed the lowest SNR. In this study, image evaluation was conducted according to the imaging conditions, and low tube voltage, tube current, and small rotation angle scan are expected to be effective in reducing radiation exposure. Based on this, the patient's exposure dose should be kept as low as possible during CBCT imaging.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.89.1-89.1
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• 2010

Since Gratzel and co-workers developed a new type of solar cell based on the nanocrystalline $TiO_2$ electrode, dye-sensitized solar cells (DSSCs) have attracted considerable attention on account of their high solar energy-to-conversion efficiencies (11%), their easy manufacturing process with low cost production compared to conventional p-n junction solar cells. The mechanism of DSSC is based on the injection of electrons from the photoexcited dye into the conduction band of nanocrystalline $TiO_2$. The oxidized dye is reduced by the hole injection process from either the hole counter or electrolyte. Thus, the electronic structures, such as HOMO, LUMO, and HOMO-LUMO gap, of dye molecule in DSSC are deeply related to the electron transfer by photoexcitation and redox potential. To date, high performance and good stability of DSSC based on Ru-dyes as a photosensitizer had been widely addressed in the literatures. DSSC with Ru-bipyridyl complexes (N3 and N719), and the black ruthenium dye have achieved power conversion efficiencies up to 11.2% and 10.4%, respectively. However, the Ru-dyes are facing the problem of manufacturing costs and environmental issues. In order to obtain even cheaper photosensitizers for DSSC, metal-free organic photosensitizers are strongly desired. Metal-free organic dyes offer superior molar extinction coefficients, low cost, and a diversity of molecular structures, compared to conventional Ru-dyes. Recently, novel photosensitizers such as coumarin, merocyanine, cyanine, indoline, hemicyanine, triphenylamine, dialkylaniline, bis(dimethylfluorenyl)-aminophenyl, phenothiazine, tetrahydroquinoline, and carbazole based dyes have achieved solar-to-electrical power conversion efficiencies up to 5-9%. On the other hand, organic dye molecules have large ${\pi}$-conjugated planner structures which would bring out strong molecular stacking in their solid-state and poor solubility in their media. It was well known that the molecular stacking of organic dyes could reduce the electron transfer pathway in opto-electronic devices, significantly. In this paper, we have studied on synthesis and characterization of dendritic organic dyes with different number of electron acceptor/anchoring moieties in the end of dendrimer. The photovoltaic performances and the incident photon-to-current (IPCE) of these dyes were measured to evaluate the effects of the dendritic strucuture on the open-circuit voltage and the short-circuit current.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.55-55
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.65-73
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• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.