• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.35T no.1
• /
• pp.29-32
• /
• 1998

The low level leakage currents in silicon oxides were investigated. The low level leakage currents were composed of a transient component and a do component. The transient component was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The do component was caused by trap assisted tunneling completely through the oxide. The low level leakage current was proportional to the number of traps generated in the oxides. The low level leakage current may be a trap charging and discharging current. The low level leakage current will affect data retention in EEPROM.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.1
• /
• pp.280-287
• /
• 2015

Three-level PWM rectifiers applied in medium voltage applications usually operate at low switching frequency to keep the dynamic losses under permitted level. However, low switching frequency brings a heavy cross-coupling between the current components $i_d$ and $i_q$ with a poor dynamic system performance and a harmonic distortion in the grid-connecting current. To overcome these problems, a mathematical model based on complex variables of the three-level voltage source PWM rectifier is firstly established, and the reasons of above issues resulted from low switching frequency have been analyzed using modern control theory. Then, a novel control strategy suitable for the current decoupling control based on the complex variables for $i_d$ and $i_q$ is designed here. The comparisons between this kind of control strategy and the normal PI method have been carried out. MATLAB and experimental results are given in detail.

• Proceedings of the KSRS Conference
• /
• v.1
• /
• pp.17-20
• /
• 2006

Three HF ocean radar stations were installed at the Soya/La Perouse Strait in the Sea of Okhotsk in order to monitor the Soya Warm Current. The frequency of the HF radar is 13.9 MHz, and the range and azimuth resolutions are 3 km and $5^{\circ}$, respectively. The radar covers a range of approximately 70 km from the coast. It is shown that the HF radars clearly capture seasonal and short-term variations of the Soya Warm Current. The velocity of the Soya Warm Current reaches its maximum, approximately 1 m $s^{-1}$, in summer, and weakens in winter. The velocity core is located 20 to 30 km from the coast, and its width is approximately 50 km. The surface transport by the Soya Warm Current shows a significant correlation with the sea level difference along the strait, as derived from coastal tide gauge records. The cross-current sea level difference, which is estimated from the sea level anomalies observed by the Jason-1 altimeter and a coastal tide gauge, also exhibits variation in concert with the surface transport and along-current sea level difference.

• Journal of Power Electronics
• /
• v.15 no.6
• /
• pp.1429-1437
• /
• 2015

A new parallel hybrid soft switching converter with low circulating current losses during the freewheeling state and a low output current ripple is presented in this paper. Two circuit modules are connected in parallel using the interleaved pulse-width modulation scheme to provide more power to the output load and to reduce the output current ripple. Each circuit module includes a three-level converter and a half-bridge converter sharing the same lagging-leg switches. A resonant capacitor is adopted on the primary side of the three-level converter to reduce the circulating current to zero in the freewheeling state. Thus, the high circulating current loss in conventional three-level converters is alleviated. A half-bridge converter is adopted to extend the ZVS range. Therefore, the lagging-leg switches can be turned on under zero voltage switching from light load to full load conditions. The secondary windings of the two converters are connected in series so that the rectified voltage is positive instead of zero during the freewheeling interval. Hence, the output inductance of the three-level converter can be reduced. The circuit configuration, operation principles and circuit characteristics are presented in detail. Experiments based on a 1920W prototype are provided to verify the effectiveness of the proposed converter.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.4
• /
• pp.269-274
• /
• 2004

Current delivery system, in which the analog current produced by a unique DAC circuit is stored into a current-memory circuit and delivered in a time-divided sequence, shows variation of output current as low as 4% in a current source data-driver IC for AM-OLED driven by a current-programmed method without any fuse repairing after fabrication. This driver IC has 54 outputs and can sink constant current as low as 3 ${\mu}A$ with 6-bit analog levels. Such a low current level without variation can hardly be obtained by an ordinary MOS transistor because the current level is in the sub-threshold region and changes exponentially with threshold voltage variation. Thus we adopted a current mirror circuit composed of bipolar transistors to supply well-controlled current within a nano-ampere range.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.8
• /
• pp.285-291
• /
• 2013

In this paper, MOS-Capacitor and MOSFET devices with a Low Level Leakage Current of oxide thickness, channel width and length respectively were to investigate the reliability characterizations mechanism of ultra thin gate oxide films. These stress induced leakage current means leakage current caused by stress voltage. The low level leakage current in stress and transient current of thin silicon oxide films during and after low voltage has been studied from strss bias condition respectively. The stress channel currents through an oxide measured during application of constant gate voltage and the transient channel currents through the oxide measured after application of constant gate voltage. The study have been the determination of the physical processes taking place in the oxides during the low level leakage current in stress and transient current by stress bias and the use of the knowledge of the physical processes for driving operation reliability.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.26 no.2
• /
• pp.96-105
• /
• 2021

Large-scale power converters consist of series or parallel module combinations. In these modular converter systems, the interleaving technique can be applied to improve capacitor reliability by reducing the ripple of the I/O current in which each module operates as a phase difference. However, when applying the interleaving technique for conventional three-level boost converters, the short-circuit period of the converter can be an obstacle. Such problem is caused by the absence of a low-level inductor of the conventional three-level boost converter. To solve this problem, a three-level boost converter with a low-level inductor is proposed and analyzed to enable interleaved operation. In the proposed circuit, the current ripple of the output capacitor depends on the neutral point connections between the modules. In this study, the ripple current is analyzed by the neutral point connections of the three-level boost converter that has a low-level inductor, and the effectiveness of the proposed circuit is proven by simulation and experiment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.11a
• /
• pp.13-16
• /
• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.27 no.5
• /
• pp.446-454
• /
• 2022

This study proposes a carrier-based pulse width modulation (PWM) method for leakage current reduction and neutral point (NP) current control in a three-phase three-level converter, which is a carrier-based PWM version of the previously proposed low-frequency common mode voltage PWM. Three groups of space vectors with the same common mode voltage are used. When the averaged NP current needs to be positive or negative, the specific groups are employed to produce low-frequency common mode voltages. The validity of the proposed PWM method is verified through experiments.

• Journal of Information Display
• /
• v.11 no.1
• /
• pp.21-23
• /
• 2010

A new level shifter using low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) for low-power applications is proposed. The proposed level shifter uses a capacitive-coupling effect and can reduce the power consumption owing to its no-short-circuit current. Its power saving over the conventional level shifter is 72% for a 3.3 V input and a 10 V output.