• JSTS:Journal of Semiconductor Technology and Science
• /
• 제9권4호
• /
• pp.240-248
• /
• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• Transactions on Electrical and Electronic Materials
• /
• 제14권1호
• /
• pp.28-31
• /
• 2013

A volcano shaped gated Si-FEA (silicon field emitter array) was simply fabricated using sputtering as a gate electrode deposition and lift-off for the removal of the oxide mask, respectively. Due to the limited step coverage of well-controlled sputtering and the high aspect ratio in Si dry etch caused by high RF power, it was possible to obtain Si FEAs with a stable volcano shaped gate structure and to realize the restriction of gate leakage current in field emission characteristics. For 100 tip arrays and 625 tip arrays, gate leakage currents were restricted to less than 1% of the anode current in spite of the volcano-shaped gate structure. It was also possible to keep the emitters stable without any failure between the Si cathode and gate electrode in field emission for a long time.

• ETRI Journal
• /
• 제31권6호
• /
• pp.725-731
• /
• 2009

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate-triggered NMOS and a gate-substrate-triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn-on speed. The proposed ESD protection devices are designed using 0.13 ${\mu}m$ CMOS technology. The experimental results show that the proposed substrate-triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn-on time of 37 ns. The proposed gate-substrate-triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.

• E2M - 전기 전자와 첨단 소재
• /
• 제10권1호
• /
• pp.26-32
• /
• 1997

The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제54권1호
• /
• pp.18-22
• /
• 2005

We have proposed and fabricated a dual gate AlGaN/GaN high electron mobility transistor (HEMT), which exhibits the low leakage current and the high breakdown voltage for the high voltage switching applications. The additional gate between the main gate and the drain is specially designed in order to decrease the electric field concentration at the drain-side of the main gate. The leakage current of the proposed HEMT is decreased considerably and the breakdown voltage increases without sacrificing any other electric characteristics such as the transconductance and the drain current. The experimental results show that the breakdown voltage and the leakage current of proposed HEMT are 362 V and 75 nA while those of the conventional HEMT are 196 V and 428 nA, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제7권4호
• /
• pp.215-220
• /
• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• 전자공학회논문지
• /
• 제50권8호
• /
• pp.285-291
• /
• 2013

본 논문은 금속 산화물 반도체의 산화막 두께, 채널 폭과 길이에 따른 실리콘 산화막의 신뢰성 특성을 연구하였다. 스트레스전류와 전이전류는 스트레스 전압에 의하여 발생된다. 스트레스 유기 누설전류는 스트레스 전압 인가 동안과 인가 후의 실리콘 산화막에 나타난다. 이때 저레벨 스트레스 전압에 의한 저레벨 누설전류는 저전압 인가 동안과 인가 후의 얇은 실리콘 산화막에서 발생한다. 저레벨 누설전류는 각각 스트레스 바이어스 조건에 따라 스트레스전류와 전이전류를 측정하였다. 스트레스 채널전류는 일정한 게이트 전압이 인가동안 측정하였고 전이 채널전류는 일정한 게이트 전압을 인가한 후에 측정하였다. 본 연구는 소자의 구동 동작 신뢰성을 위하여 저레벨 스트레스 바이어스 전압에 의한 스트레스 전류와 전이전류가 발생되어 이러한 저레벨 누설전류를 조사하였다.

• 한국전기전자재료학회논문지
• /
• 제16권12호
• /
• pp.1065-1070
• /
• 2003

HTO(High Temperature Oxide) films are mainly used as a gate insulator for polysilicon thin film transistors(Poly-Si TFT's). The HTO films, however, show the demerits of a high leakage current and a low electric breakdown voltage comparing with conventional thermal oxides even though they have a better surface in roughness than the thermal oxides. In this paper, we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's. The leakage current and electric breakdown voltage of the ONO and HTO were measured. The drain current variation of poly-Si TFT's with a variety of gate insulators was observed. The thickness optimization in ONO films was carried out by studying I$\_$on/I$\_$off/ ratio of the poly-Si TFT's as a function of the thickness of ONO film adopted as gate insulator.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2005년도 추계종합학술대회
• /
• pp.881-883
• /
• 2005

게이트의 길이가 100nm 이하인 경우에는 절연막의 두께도 1.5nm 이하로 스케일링되며, 도핑농도도 증가하게 되기 때문에 소자의 문턱전압 변화, 게이트 절연막의 터널링에 의한 허용치 이상의 누설전류의 발생 등 여러 가지 문제점이 발생될 수 있다. SiO$_2$ 유전체는 1.5nm 두께 이하에서 터널링 전류가 1A/cm$^2$ 이상이 될 것으로 예상되므로, 게이트 절연막으로 사용될 수 없다. 본 연구에서는 이러한 터널링에 의한 누설전류의 영향을 줄이기 위하여 더블게이트 MOSFET(DGMOSFET)를 고안하였다. SiO$_2$ 유전체의 두께가 1nm이하에서도 이러한 누설전류의 영향을 줄일 수 있게 되었다. 그러나 나노 크기의 소자를 개발하기 위해서는 유전율이 매우 큰 게이트 절연체가 개발되어야 한다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.579-580
• /
• 2006

Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.