1 |
P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, 'Selective gatelength biasing for costeffective runtime leakage control,' in Proc. Design Automat. Conf., June 2004, pp. 327-330
|
2 |
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. SangiovanniVincentelli, 'SIS: a system for sequential circuit synthesis,' Tech. Rep., UCBIERL M92/41, U. C. Berkeley, May 1992
|
3 |
W. Zhao and Y. Cao, 'New generation of predictive technology model for sub-45nm design exploration,' in Proc. Int'l Symp. on Quality Electronic Design, Mar. 2006, pp. 585-590
|
4 |
K. Keutzer, 'DAGON: technology binding and local optimization by DAG matching,' in Proc. Design Automat. Conf, June 1987, pp. 341-347
|
5 |
S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Ricc'o, 'Estimate of signal probability in combinational logic networks,' in Proc. European Test Conf., Apr. 1989, pp. 132-138
|
6 |
D. Lee, W. Kwong, D. Blaauw, and D. Sylvester, 'Analysis and minimization techniques for total leakage considering gate oxide leakage,' in Proc. Design Automat. Conf., June 2003,pp. 175-180
|
7 |
S. G. Narendra and A. Chandrakasan, Eds., Leakage in Nanometer CMOS Technologies, Springer, 2005
|