• 제목/요약/키워드: Low Delay

검색결과 1,834건 처리시간 0.028초

저지연 서비스를 위한 Multi-access Edge Computing 스케줄러 (Multi-access Edge Computing Scheduler for Low Latency Services)

  • 김태현;김태영;진성근
    • 대한임베디드공학회논문지
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    • 제15권6호
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    • pp.299-305
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    • 2020
  • We have developed a scheduler that additionally consider network performance by extending the Kubernetes developed to manage lots of containers in cloud computing nodes. The network delay adapt characteristics of the compute nodes were learned during server operation and the learned results were utilized to develop placement algorithm by considering the existing measurement units, CPU, memory, and volume together, and it was confirmed that the low delay network service was provided through placement algorithm.

Energy-efficient Low-delay TDMA Scheduling Algorithm for Industrial Wireless Mesh Networks

  • Zuo, Yun;Ling, Zhihao;Liu, Luming
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제6권10호
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    • pp.2509-2528
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    • 2012
  • Time division multiple access (TDMA) is a widely used media access control (MAC) technique that can provide collision-free and reliable communications, save energy and bound the delay of packets. In TDMA, energy saving is usually achieved by switching the nodes' radio off when such nodes are not engaged. However, the frequent switching of the radio's state not only wastes energy, but also increases end-to-end delay. To achieve high energy efficiency and low delay, as well as to further minimize the number of time slots, a multi-objective TDMA scheduling problem for industrial wireless mesh networks is presented. A hybrid algorithm that combines genetic algorithm (GA) and simulated annealing (SA) algorithm is then proposed to solve the TDMA scheduling problem effectively. A number of critical techniques are also adopted to reduce energy consumption and to shorten end-to-end delay further. Simulation results with different kinds of networks demonstrate that the proposed algorithm outperforms traditional scheduling algorithms in terms of addressing the problems of energy consumption and end-to-end delay, thus satisfying the demands of industrial wireless mesh networks.

저전력과 크로스톡 지연 제거를 위한 버스 인코딩 (Bus Encoding for Low Power and Crosstalk Delay Elimination)

  • 여준기;김태환
    • 한국정보과학회논문지:시스템및이론
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    • 제29권12호
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    • pp.680-686
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    • 2002
  • 딥 서브 마이크론 (DSM: deep-submicron) 설계에서는 버스에서 선들 간의 커플링 효과는 크로스톡 지연, 노이즈, 전력 소모와 같은 심각한 문제를 야기 시킨다. 버스 인코딩에 대한 대부분의 이전 연구들은 버스에서의 전력 소모를 최소화하거나 크로스톡 지연을 최소화하는데 초점을 맞추고 있지만 모두를 고려한 방법은 보이지 않는다. 이 논문에서, 우리는 버스에서의 전력 소모 최소화와 크로스톡 지연 방지를 동시에 고려한 새로운 버스 인코딩 알고리즘을 제안하였다. 우리는 이 문제를 공식화하여, 자체 천이와 상호 천이의 가중 합 문제를 풂으로써 해결하였다. 여러 벤치마크 설계를 이용한 실험으로부터 제안한 인코딩 방법을 이용할 경우, 크로스톡 지연을 완전히 제거할 뿐 아니라 이전의 방법들을 사용한 것 보다 최소 15% 이상 적은 전력을 소모하였음을 보았다.

새로운 구간 분해 방법을 이용한 구간 시변지연을 갖는 선형시스템의 안정성 (Stability of Linear Systems with Interval Time-varying Delay via New Interval Decomposition)

  • 김진훈
    • 전기학회논문지
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    • 제60권9호
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    • pp.1748-1753
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    • 2011
  • In this paper, we consider the stability of linear systems with an interval time-varying delay. It is known that the adoption of decomposition of delay improves the stability result. For the interval time-delay case, they applied it to the interval of time-delay and got less conservative results. Our basic idea is to apply the general decomposition to the low limit of delay as well as interval of time-delay. Based on this idea, by using the modified Lyapunov-Krasovskii functional and newly derived Lemma, we present a less conservative stability criterion expressed as in the form of linear matrix inequality(LMI). Finally, we show, by well-known two examples, that our result is less conservative than the recent results.

Delay Monitor Scheme을 사용한 Register Controlled Delay-locked Loop (Register Controlled Delay-locked Loop using Delay Monitor Scheme)

  • 이광희;노주영;손상희
    • 한국전기전자재료학회논문지
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    • 제17권2호
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    • pp.144-149
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    • 2004
  • Register Controlled DLL with fast locking and low-power consumption, is described in this paper. Delay monitor scheme is proposed to achieve the fast locking and inverter is inserted in front of delay line to reduce the power consumption, also. Proposed DLL was fabricated in a 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS technology. The proposed delay monitor scheme enables the DLL to lock to the external clock within 4 cycles. The power consumption is 36㎽ with 3V supply voltage at 34MHz clock frequency.

A Low-Jitter DLL-Based Clock Generator with Two Negative Feedback Loops

  • Choi, Young-Shig;Park, Jong-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권4호
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    • pp.457-462
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    • 2014
  • This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

저전압 SRAM 의 고속동작을 위한 전류감지 증폭기 (A current sense amplifier for low-voltage and high-speed SRAM)

  • 박현욱;심상원;정연배
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2005년도 추계종합학술대회
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    • pp.727-730
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    • 2005
  • In this paper, we propose a new current sense amplifier for low-voltage, high-speed SRAM. As a supply voltage is reduced, a sensing delay is increased owing to reduced cell read current. It causes a low-speed operation in SRAM. To overcome this problem, we present a new current sense amplifier which consists of the current-mirror type circuit with feedback structure. For demonstration, a 0.8-V, 256-Kb SRAM incorporating the proposed current sense amplifier has been designed with $0.18-{\mu}m$ CMOS technology. The simulation results show 15.6ns of the sensing delay reduction in comparison with a previous current sense amplifier and 11.5ns of the sensing delay reduction in comparison with a voltage sense amplifier.

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Coupled Line Phase Shifters and Its Equivalent Phase Delay Line for Compact Broadband Phased Array Antenna Applications

  • Han, Sang-Min;Kim, Young-Sik
    • Journal of electromagnetic engineering and science
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    • 제3권1호
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    • pp.62-66
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    • 2003
  • Novel coupled line phase shifters and its equivalent phase delay line for compact broadband phased array antennas are proposed. These phase control circuits are designed to be less complex, small size and to use a less number of active devices. The phase shifter is able to control a 120$^{\circ}$ phase shift continuously, and the phase delay line for a reference phase has a fixed 60$^{\circ}$ shifted phase. Both have the low phase error of less than $\pm$3.5$^{\circ}$ and the low gain variations of less than 1 ㏈ within the 300 MHz bandwidth. These proposed circuits are adequate to form the efficient beam-forming networks with compactness, broadband, less complexity, and low cost.

공압능동제어를 이용한 저주파 영역에서의 공압제진대 제진성능 개선에 대한 연구 (Performance Enhancement of Pneumatic Vibration Isolation Tables in Low Frequency by Active Control)

  • 오기용;이정훈;김광준;신윤호
    • 한국소음진동공학회:학술대회논문집
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    • 한국소음진동공학회 2006년도 추계학술대회논문집
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    • pp.903-908
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    • 2006
  • As environmental vibration requirements on precision equipment become more stringent. use of pneumatic isolators has become more popular and their performance is subsequently required to be further improved. Dynamic performance of passive pneumatic isolators is related to various design parameters in a complicated manner and, hence, is very limited especially in low frequency range by volume of chambers. In this study, an active control technique, so called time delay control which is considered to be adequate for a low frequency or nonlinear system, is applied to a single chamber pneumatic isolator. The procedure of applying the time delay control law to the pneumatic isolator is presented and its effectiveness in enhancement of transmissibility performance is shown based on simulation and experiment. Comparison between passive and active pneumatic isolators is also presented.

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Channel-Adaptive Rate Control for Low Delay Video Coding

  • Lee, Yun-Gu
    • IEIE Transactions on Smart Processing and Computing
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    • 제5권5호
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    • pp.303-309
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    • 2016
  • This paper presents a channel-adaptive rate control algorithm for low delay video coding. The main goal of the proposed method is to adaptively use the unknown available channel bandwidth while reducing the end-to-end delay between encoder and decoder. The key idea of the proposed algorithm is for the status of the encoder buffer to indirectly reflect the mismatch between the available channel bandwidth and the generated bitrate. Hence, the proposed method fully utilizes the unknown available channel bandwidth by monitoring the encoder buffer status. Simulation results show that although the target bitrate mismatches the available channel bandwidth, the encoder efficiently adapts the given available bandwidth to improve the peak signal-to-noise ratio.