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Bus Encoding for Low Power and Crosstalk Delay Elimination  

여준기 (한국과학기술원 전자전산학과)
김태환 (한국과학기술원 전자전산학과)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.29, no.12, 2002 , pp. 680-686 More about this Journal
Abstract
In deep-submicron (BSM) design, coupling effects between wires on the bus cause serious problems such as crosstalk delay, noise, and power consumption. Most of the previous works on bus encoding are targeted either to minimize tile power consumption on bus or to minimize the crosstalk delay, but not both. In this paper, we propose a new bus encoding algorithm that minimizes the power consumption on bus and eliminates the crosstalk delay simultaneously. We formulate and solve the problem by minimizing a weighted sum of the self transition and cross-coupled transition activities on bus From experiments using a set of benchmark designs. it is shown that the proposed encoding technique consumes at least 15% less power over the existing techniques, while completely eliminating the crosstalk delay.
Keywords
VLSI CAD; VLSI CAD; Bus Encoding; Low flower; Crosstalk Delay Elimination;
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