• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 1991.04a
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• pp.95-98
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• 1991

회전 기기의 이상으로 인하여 발생하는 진동은 축 회전속도의 고주파 성분 (super-harmonic)이나 또는 분수조파 성분(sub-harmonic)으로 나타나는 경 우가 대부분이기 때문에 회전기기의 진동을 주파수 영역에서 해석함에 있어 파워 스펙트럼의 주파수 축을 Hz로 나타내기보다는 축 회전속도의 order로 써 나타내는 것이 매우 유용하다. 스펙트럼을 order로써 나타내기 위해서는 샘플링 시간을 축 회전속도와 동기(synchronization)시켜야 하는데 이 방법으 로는 회전축에 엔코더(encorder)를 부착하여 엔코더에서 발생하는 펄스 신호 를 이용하여 샘플링하는 방법과 order tracking 필터를 이용하는 방법이 있 다. 그러나 전자의 방법은 원하는 회전축마다 엔코더를 부착하여야 하며 경 우에 따라서는 엔코더를 부착하기가 어려운 경우도 있으며, 회전기기의 운전 개시나 종료시처럼 회전속도가 급격히 변화하는 경우에는 낮은 주파수에서 중첩(aliasig)에 의한 오차가 수반될 수도 있다. 후자의 방법은 order tracking 필터 이외에도 여러 부수장비가 필요하며 기준 주파수(즉 회전속 도)가 급격히 변화하는 경우 PLL(phase locked loop)에서 tracking 오차가 발생된다. 최근에 발표된 논문에서 일정한 시간간격으로 샘플링한 데이터들 로부터 신호를 재합성하여 회전축의 속도와 동기가 되도록 재 샘플링함으로 서 스펙트럼의 주파수를 회전속도의 order로써 나타내는 방법을 제시하였다. 그러나 위 논문에서는 신호의 재합성에 필요한 재합성 필터(reconstruction filter)의 설계 방법에 대하여 구체적인 언급이 없이 다만 결과만을 논하였다. 따라서 본 논문에서는 재합성 필터의 설계 방법에 대하여 구체적인 방법을 제시하고 또한 동기화 샘플링의 장점 및 고려 사항에 대하여 고찰하였다. 고려한 능동 소음제어 에 대해 연구하였다. 경량화 추세에 따라 지반이나 케이싱이 경량이거나 유연하여 회전축과 동적으로 연성된 경우 회전축-베어링-지반으로 이루어진 2중구조의 회전축 계 동특성을 해석할 수 있는 프로그램을 개발하므로서 회전 기계류의 진동 전반에 걸친 문제점에 대한 그 원인과 현상을 명확히 분석하여 국내의 전기 계류의 보다 신뢰성있는 설계 및 제작자료를 확보하는데 기여할 수 있게 하 였다.존의 small molecular Gd-chelate에 비해 매우 큼을 알 수 있었다. MnPC는 간세포에 흡수된 후 담도계로 배출되는 간특이성 조영제임을 확인하였다. 장비 내에서 반복 시행한 평균값의 차이는 대체적으로 유의한 차이가 없었으나, 다른 장비에서 반복 시행한 장비간의 사이에는 유의한 차이가 있는 경우가 더 많았다. 따라서 , MRS 검사를 소뇌나 뇌교의 어떤 절환에 적용하기 전에 각 장비 마다 정상 기준치를 반드시 얻은 후에 이상여부를 판 정하는 것이 필수적이라고 생각된다.EX> 이상이 적절한 진단기준으로 생각되었다. $0.4{\;}\textrm{cm}^3$ 이상의 좌우 부피차를 보이는 모든 증례에서 육안적으로도 해마위축이 뚜렷이 나타났다. 결론 : MR영상을 이용한 해마의 부피측정은 해마경화증 환자의 진단에 있어 육안적인 MR 진단이 어려운 제한된 경우에만 실제적 도움을 줄 수 있는 보조적인 방법으로 생각된다.ofile whereas relaxivity at high field is not affected by τS. On the other hand, the change in τV does not affect low field profile but strongly in fluences on both inflection fie이 and the maximum relaxivity value. The re

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.5
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• pp.431-439
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• 2013

A cooling system is adopted to control the thermal load from the avionic equipments in an aircraft for stable operation. In this study, an avionic cooling system was designed and manufactured by adopting a vapor compression cycle with a closed-loop air-circulation system to investigate the operating characteristics of an alternative refrigerant. The performance characteristics of a cooling system adopting R236fa as an alternative refrigerant were experimentally determined by varying the refrigerant charging amount, expansion valve opening, and compressor rotation speed. The experimental results were analyzed and compared with those of a cooling system adopting R124 as a refrigerant. The possibility of the adoption of R236fa as an alternative refrigerant was verified, and design solutions were suggested to improve the system efficiency.

• Journal of Korean Society of Transportation
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• v.24 no.7 s.93
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• pp.41-51
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• 2006

In this paper, a fundamental study on the characteristics of traffic accidents according to the alignment and traffic conditions on the ramp of freeway is addressed. The macro-and-micro scope analysis of characteristics about traffic accidents on the trumpet-IC ramps is conducted depending on the entering and exit ramp types under the various conditions of traffic volume and alignment And it is turned out that the conditions of alignment. such as radius, differences of curvatures, and main road grade, and traffic volume relate to the ramp accidents of trumpet IC according to ramp types, such as direction, semi-direction, and loop. Macroscopically, AR (Accident Rate) according to trumpet IC types, A and B, is analyzed nearly equal, but Number of accidents occurred in IC type B shows about 1.5 times higher than type A. And AR of exit ramps shows three times more than entrance ramps. Microscopically, ARs for each exit-ramp type, according to the increment of traffic volume, the difference of curvatures. and the first radius, exponentially decrease respectively. But relationships between AR and the second radius or exit ramp shows inverted U-shaped. AR according to main-road grade Peaks between -1.5% and -0.5%. It is expected that the developed models not only are employed to make design of trumpet-IC ramp more cost-efficiently and safely, but also contribute to making alternatives to the reduction of traffic accidents on trumpet IC ramps under the conditions of high traffic accident rate.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.6
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• pp.64-72
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• 2010

In general, due to the interactions among subsystems, it is difficult to design an decentralized controller for nonlinear interconnected systems. In this study, the model of nonlinear interconnected systems is studied via decentralized fuzzy control method with time delay and polytopic uncertainty. First, the nonlinear interconnected system is represented by an equivalent Takagi-Sugeno type fuzzy model. And the represented model can be rewritten as Parameterized Linear Matrix Inequalities(PLMIs), that is, LMIs whose coefficients are functions of a parameter confined to a compact set. We show that the resulting fuzzy controller guarantees the asymptotic stability and disturbance attenuation of the closed-loop system in spite of controller gain variations within a resulted polytopic region by example and simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.34-41
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• 2011

This paper presents a wide tuning range, fine-resolution DCO (Digitally Controlled Oscillator) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. To cover the wide tuning range, an automatic three-step coarse tuning scheme is proposed. The DCO total frequency tuning range is 1.4 GHz (2.1 GHz to 3.5 GHz), it is 58 % at 2.4 GHz. An effective frequency resolution is 0.14 kHz/LSB. The proposed DCO is implemented in 0.13 ${\mu}m$ CMOS process. The total power consumption is 6.6 mW from a 1.2 V supply voltage. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.25-32
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• 2005

In this papers, we first, therefore, designed VCO(voltage controlled oscillator) that is composed of the dielectric resonator and the varactor diode, and then designed and fabricated PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The measured results of the fabricated PLDRO at 12.05 [GHz] show the output power is 13.54 [dBm], frequency tuning range approximately +/- 7.5 [MHz], and Power variation over the tuning range less than 0.2 [dB], respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 [dBc/Hz] at 100 [KHz] offset from carrier, and The second harmonic suppression is less than -41.49 [dBc]. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.40 no.11
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• pp.979-986
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• 2016

The tripod shafts of constant-velocity joint are used in both the trains KTX and KTX-sanchon. It is an important component that connects the motor reduction unit and the axle reduction unit in a power bogie. The tripod shaft not only transmits drive and brake torque in the rotational direction, but also slides in the axial direction. If the drive system is loaded with an excessive torque, the fuse part of the shaft will be fractured firstly to protect the other important components. In this study, a rig was developed for conducting torsion tests on the tripod shaft, which is a type of mechanical fuse. The tripod shafts were subjected to torsional fracture test and torsional fatigue test on the rig. The weak zone of the tripod shaft was identified, and its fatigue life was predicted using finite element analysis (FEA). After analyzing the FEA results, design solutions were proposed to improve the strength and fatigue life of the tripod shaft. Furthermore, the deterioration trend and time for failure of the tripod shaft were verified using the hysteresis loops which had been changed with the advancement of the torsional fatigue test.