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http://dx.doi.org/10.5392/JKCA.2010.10.2.072

Design of a Clock and Data Recovery Circuit Using the Multi-point Phase Detector  

Yoo, Sun-Geon ((주)에이디텍)
Kim, Seok-Man (충북대학교 정보통신공학과)
Kim, Doo-Hwan (충북대학교 정보통신공학과)
Cho, Kyoung-Rok (충북대학교 전자정보대학)
Publication Information
The Journal of the Korea Contents Association / v.10, no.2, 2010 , pp. 72-80 More about this Journal
Abstract
The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.
Keywords
Clock and Data Recovery(CDR); Phase Locked Loop(PLL); Phase Detector(PD);
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