1 |
B. Razavi, "Challenges in the design of
high-speed clock data recovery circuit," IEEE
Communication Magazine, pp.94-101, 2002(8).
DOI
ScienceOn
|
2 |
D. Rennie and M. Sachdev, "Comparative
robustness of CML phase detectors for clock
and data recovery circuits," in Proc. IEEE Int.
Symp. on Quality Electronic Design,
pp.305-310, 2007(3).
DOI
|
3 |
Z. W. T. Hui and T. A. Kwasniewski, "A
10-Gb/s CMOS sample-and-hold phase
detector using dual substrate technique," in
Proc. IEEE Conf. on Electrical and Computer
Engineering, Vol.3, pp.1761-1764, 2004.
DOI
|
4 |
K. S. Yeo, A. Cabuk, R. Wu, M. A. Do, J. G. Ma,
X. P. Yu, and G. Q. Yan, “Non-sequential linear
CMOS phase detector for CDR applications," in
Proc. IEE Circuits, Devices and Systems,
Vol.152, No.6, pp.667-672, 2005(12).
DOI
|
5 |
F. Gardner, "Charge-pump phase-lock loops,"
IEEE Trans. on Communications, Vol.28, No.11,
pp.1849-1858, 1980(11).
DOI
|
6 |
R. Jacob baker, CMOS circuit design, layout,
and simulation, IEEE press, 2005.
|
7 |
I. A. Young, J. K. Greason, and K. L. Wong, "A
PLL clock generator with 5 to 110 MHz of lock
range for microprocessors," IEEE J. Solid-State
Circuits, Vol.27, No.11, pp.1599-1607, 1992.
DOI
ScienceOn
|
8 |
R. Zhang and G. S. La Rue, “Clock and data
recovery circuits with fast acquisition and low
jitter,” IEEE Workshop on Microelectronics and
Electron Devices, pp.48-51, 2004.
DOI
|
9 |
W. Liu, L. Xiao, and L. Yang, "1.25 Gb/s low
jitter dual-loop clock and data recovery circuit,"
in Proc. IEEE ASIC, pp.311-314, 2007(10).
DOI
|
10 |
M. Saffari, M. Atarodi, and A. Tajalli, "A 1/4
rate linear phase detector for PLL-based CDR
Circuits," in Proc. IEEE ISCAS, pp.3281-3284,
2006(5).
DOI
|
11 |
J. D. H. Alexander, "Clock recovery from
random binary signals," Electronics Letters,
Vol.11, No.22, pp.541-542, 1975(10).
DOI
ScienceOn
|
12 |
J. S. Lee and B. S. Kim, "A low-noise
fast-lock phase-locked loop with adaptive
bandwidth Control," IEEE J. Solid-State
Circuits, Vol.35 No.8, pp.1137-1145, 2000(8).
DOI
ScienceOn
|
13 |
C. R. Hogge, "A self-correcting clock recovery
circuit," IEEE Trans. on Electron Devices,
Vol.32, No.12, pp.2704-2706, 1985(12).
DOI
ScienceOn
|