• ETRI Journal
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• v.42 no.5
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• pp.790-798
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• 2020

Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.

• Journal of IKEEE
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• v.18 no.1
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• pp.37-44
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• 2014

In this paper we present an LDO based on an error amplifier. The designed error amplifier has a gain of 89.93dB at low frequencies. This amplifier's Bandwidth is 50.8MHz and its phase margin is $59.2^{\circ}C$. Also we proposed a BGR. This BGR has a low output variation with temperature and its PSRR at 1 KHz is -71.5dB. For a temperature variation from $-40^{\circ}C$ to $125^{\circ}C$ we have just 9.4mV variation in 3.3V LDO output. Also it is stable for a wide range of output load currents [0-200mA] and a $1{\mu}F$ output capacitor and its line regulation and especially load regulation is very small comparing other papers. The PSRR of proposed LDO is -61.16dB at 1 KHz. Also we designed it for several output voltages by using a ladder of resistors, transmission gates and a decoder. Low power consumption is the other superiority of this LDO which is just 1.55mW in full load. The circuit was designed in $0.35{\mu}m$ CMOS process.

• Journal of IKEEE
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• v.22 no.2
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• pp.384-392
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• 2018

A multiple-output LDO regulator is a good choice in terms of the efficiency in embedded systems requiring various supply voltages. A small feedback factor in LDO incurs the long settling time, resulting in large ripples in the time-multiplexing strategy. A new proposed topology enhances the settling time, and hence the ripples by incorporating the constant feedback factor with different reference voltages. The simulation results of a prototype design in a standard $0.35{\mu}m$ CMOS process verify that the proposed strategy enhances the settling time and ripple characteristic by more than doubled than a conventional circuit using the feedback factor of less than 0.4.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.1-6
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• 2016

In this paper, we introduce the characteristics of a vertical PNP transistor that improves start current by decreasing quiescent current with suppressing the parasitic transistor. In order to suppress the parasitic effect, we designed a vertical PNP transistor which suppresses parasitic PNP transistor by using the "DN+ links" without changing the circuit and made a LDO regulator using a standard IC processor. HFE of the fabricated parasitic PNP transistor decreased from conventional 18 to 0.9. Starting current of the LDO regulator made of the vertical PNP transistor using the improved "DN+ linked" structure is reduced from the conventional starting current of 90mA to 32mA. As the result, we developed a LDO regulator which consumes lower power in the standby state.

• Journal of IKEEE
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• v.20 no.3
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• pp.318-321
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• 2016

As IoT industry are growing fast, The importance of power management system is also being magnified. CMOS High power-supply rejection ratio(PSRR) Low-dropout(LDO) regulator is achieved by the proposed ripple Subtractor, Feed-forward capacitor and OTA in this paper. The LDO is implemented in $0.18-{\mu}m$ CMOS technology. With the proposed structures, in the maximum loading of 40mA, Simulation result achieves PSRR of -73.4dB at 500kHz and PSRR better than -40dB when frequency is below 10MHz with $6.8-{\mu}F$ output capacitor.

• Journal of IKEEE
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• v.27 no.3
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• pp.333-339
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• 2023

The global market for wearable devices is growing, driving demand for efficient PMICs. Wearable PMICs must be highly energy-efficient despite limited hardware resources. Advancements in process technology enable low-power consumption, but traditional analog LDO regulators face challenges with reduced power supply voltage. In this paper, a novel ADC design with a 3-bit continuous-time flash ADC for the coarse loop and a 5-bit discrete-time SAR ADC for the fine loop is proposed for digital LDO, achieving a 34.78 dB SNR and 5.39 bits ENOB in a 55-nm CMOS technology.

• 전자공학회논문지 IE
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• v.48 no.4
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• pp.13-18
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• 2011

In this paper, we have examined electrical characteristics of LDO regulator according to the process variation using a 1 ${\mu}m$ 20 V high voltage CMOS process. The electrical analysis of LDO regulator have been performed with three kind of SPICE parameter sets (Typ : typical, FF : fast, SS : slow) by process variation which cause change of SPICE parameter such as threshold voltage and effective channel length of MOS devices. From simulation results, we confirmed that in case of SS type SPICE parameter set, the LDO regulator has 3.6 mV/V line regulation, 0.4 mV/mA load regulation and 0.86 ${\mu}s$ output voltage settling time. And in case of Typ type SPICE parameter set, the LDO regulatorhas 4.2 mV/V line regulation, 0.44 mV/mA load regulation and 0.62 ${\mu}s$ output voltage settling time. Finally, in the FF type SPICE parameter set, the LDO regulator has 7.0 mV/V line regulation, 0.56 mV/mA load regulation and 0.27 ${\mu}s$ output voltage settling time.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2729-2734
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• 2011

In this paper, an active replica Low-dropout(LDO) regulator with DC voltage matching circuit is presented. In order to match the voltage between replica and output of regulator, DC voltage matching circuit is designed. The active replica low dropout regulator has higher Power Supply Rejection(PSR) than that of conventional regulator. The designed DC voltage matching circuit can reduce the drawback that may be occurred in replica regulator. And using fully active element in regulator can reduce the chip area and heat noise with resistor. As results of HSPICE simulation with 0.35um CMOS parameter, the designed active replica LDO regulator achieves Power Supply Rejection, -28@10Hz better than -17@10Hz of conventional replica regulator without DC matching circuit. And the output voltage is 3V.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.9
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• pp.6247-6253
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• 2015

This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix $0.18{\mu}m$ CMOS parameters. Chip layout size is $500{\mu}m{\times}150{\mu}m$. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.263-271
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• 2013

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in $0.18-{\mu}m$ high voltage CMOS, the proposed LDO shows up to 200 mA load current with 0.2 V dropout voltage for $1{\mu}F$ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 mV, $7.5{\mu}A$, and higher than 1 MHz, respectively.