• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.844-850
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• 2002

Linearly graded profiles on the field area oxide are frequently used in power integrated circuits to reduce the surface electric field when power devices are operated in forward or reverse blocking modes. It is shown here that tapered windows can be made using the difference of etch rates between the bottom and the top layer of TEOS film. Annealed TEOS films are etched at a lower rate than the TEOS film without annealing Process. The fast etching layer results in window walls having slopes in the range of 25$^{\circ}$∼ 80$^{\circ}$ with respect to the wafer surface. Taper etching technique by annealing the TEOS film applies to high voltage LDMOS, which is compatible with CMOS process, due to the minimum changes in both of design rules and thermal budget.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.13-16
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• 2002

In this study, the electrical characteristics of 100v-Class LDMOSFET for high temperature applicat -ions such as electronic control systems of automo -biles and motor driver were investigated. Measurement data are taken over wide range of temperature(300k-SOOK) and various gate length(1.5 #m-3.0#m, step 0.3). In high temperature condition(>500k), drain current decreased over 30%, and specific on- resistance increased about three times in comparison with room temperature. Moreover, the ratio ROJBV, a figure of merit of the device, increased with increasing temperature.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1077-1080
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• 2003

This paper show the measured result of electrical characteristics of SOI-LDMOSFET that is one of the high voltage devises. Especially, we observed changes of breakdown voltage, threshold voltage, on-resistance, drain current, and transconductance in accordance with drift length, main parameter of LDMOSFET. Also, we achieved reliability analysis about device operation in high temperature environment because LDMOS is applied to smart power IC.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1057-1060
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• 2003

This paper is about the optimized fabricated parameter in the EDMOSFET(Extended drain MOSFET) with a various temperature. As we know, the two important factors of EDMOSFET parameters are breakdown voltage and on Resistance. So, we have aims of the power EDMOSFET design to have high breakdown voltage and low on resistance. Thus in this paper, we will show the figure of merit in LDMOS (BV/Ron) in accordance with increase in temperature(300K-500K, step:50K), and measure electronic characteristics of power EDMOSFET. As a result, the important factors in design of EDMOS are temperature and Lg.

• ETRI Journal
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• 제20권1호
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• pp.37-45
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• 1998

Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2006년도 전기학술대회논문집
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• pp.301-302
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• 2006

초고주파 전력 증폭기의 바이어스 전압을 조절하여 온도 변화에 따른 드레인(Drain) 전류의 변화를 억제하기 위한 저가의 능동 바이어스 모듈을 개발한다. 능동 바이어스 모듈을 5 W급 초고주파 전력증폭기에 적용하였을 경우, $0{\sim}60^{\circ}C$까지의 온도변화에 대하여 소모전류 변화량은 0.1 A 이하로 되어야 한다. 본 기술 개발 대상인 능동 바이어스 모듈의 성능 시험을 위한 대상 전력증폭기는 $2.11{\sim}2.17GHz$ 주파수 대역에서 32 dB 이상의 이득과 ${\pm}0.1\;dB$ 이하의 이득 평탄도, -15 dB 이하의 입.출력 반사손실을 가진다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.239-242
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• 1999

In this paper, we report the process/device design of high-speed, high-voltage SOI smart power IC for mobile communication system, high-speed HDD system and the electronic control system of automobiles. The high voltage LDMOS with 70V breakdown voltage under 0.8${\mu}{\textrm}{m}$ design rule, the high voltage bipolar with 40V breakdown voltage for analog signal processing, the high speed bipolar with cut-off frequency over 20㎓ and LDD NMOS for high density were proposed and simulated on a single chip by the simulator DIOS and DESSIS. And we extracted the process/device parameters of the simulated devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.227-231
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• 2008

A latchup-free design based on the lateral diffused MOS (LDMOS) adopting the "Darlington" approaches was designed. The use of Darlington configuration as the trigger circuit results in the reduction of the size of the circuit when compared to the conventional inverter driven RC-triggered MOSFET ESD power clamp circuits. The proposed clamp was fabricated using a $0.35{\mu}m$ 60V BCD (Bipolar CMOS DMOS) process and the performance of the proposed clamp was successfully verified by TLP (Transmission Line Pulsing) measurements.

• Transactions on Electrical and Electronic Materials
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• 제10권6호
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• pp.189-192
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• 2009

The leakage current in a CMOS image sensor (CIS) can have various origins. Leakage current investigations have focused on such things as cobalt-salicide, source and drain scheme, and shallow trench isolation (STI) profile. However, there have been few papers examining the effects on leakage current of nitride stringers that are formed by gate sidewall etching. So this study reports the results of a series of experiments on the effects of a nitride stringer on real display images. Different step heights were fabricated during a STI chemical mechanical polishing process to form different nitride stringer sizes, arsenic and boron were implanted in each fabricated photodiode, and the doping density profiles were analyzed. Electrons that moved onto the silicon surface caused the dark leakage current, which in turn brought up the speckle defect on the display image in the CIS.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.271-273
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• 2007

본 논문에서는 TV나 Audio등에 사용되는 2채널 30W급 Class-D amplifier를 동부하이텍의 0.35um BD350BA 공정을 사용하여 디지털 방식의 Class-D amplifier 출력단 구동에 적합하도록 설계하였다. 출력단은 Bootstrap 전원을 사용한 N-N type의 30V LDMOS 내장형이며 각각 $250m{\Omega}$의 턴 온 저항을 갖게 설계 되었다. THD+N 특성개선을 위한 Dead time 및 Delay 조정회로를 내장하였으며 보호회로로는 Over current, Over temperature, UVLO 가 있다.