Tapered Etching of Field Oxide with Various Angle using TEOS |
김상기
(한국전자통신연구부 집적회로연구부)
박일용 (한국전자통신연구부 집적회로연구부) 구진근 (한국전자통신연구부 집적회로연구부) 김종대 (한국전자통신연구부 집적회로연구부) |
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High-voltage power integrated circuit technology using SOI for driving plasma display panels
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DOI ScienceOn |
2 |
유도결합 플라즈마를 이용한 YMnO₃ 박막의 건식식각 특성 연구
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과학기술학회마을 |
3 |
Via Contact 형성을 위한 산화막 식각 공정의 신경망 모델
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과학기술학회마을 |
4 |
Improvement on p-channel SOI LDMOS transistor by adaping a new tapered oxide technique
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DOI ScienceOn |
5 |
Redistribution of diffused boron in silicon by thermal oxidation
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DOI |
6 |
Breakdown voltage enhancement of the p-n junction by self-aligned double diffusion process through a tapered SiO2 implant mask
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DOI ScienceOn |
7 |
Tapered windows in phosphorus-doped SiO₂ by ion implantation
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DOI ScienceOn |
8 |
단결정 6H-SiC 광전화학 습식식각에 대한 연구
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과학기술학회마을 |
9 |
Characterization of via etch in CHF₃/CF₄ magnetically enhanced relative ion etching using neural networks
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Silicon Processing for the VLSI Era
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12 |
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13 |
Failure analisis of evaporated metal interconnections at contact window
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DOI ScienceOn |