• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.386-386
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• 2012

We studied a bilateral switching device for spin transfer torque (STT-MRAM) based on 3D device simulation. Metal/P/N+or Metal/N/P+ junction device with $30{\times}30nm2$ area which is composed of one side schottky junction at Metal/P/N+ and Metal/N/P+ provides sufficient bidirectional current flow to write data by a drain induced barrier lowering (DIBL). In this work, Junction device confirmed that write current is more than 30 uA at 2 V, It is also has high on-off ratio over 105 under read operation. Junction device has good process feasibility because metal material of junction device could have been replaced by bottom layer of MTJ. Therefore, additional process to fabricate two outer terminals is not need. so, it provides simple fabrication procedures. it is expected that Metal/P/N+ or Metal/N/P+ structure with one side schottky junction will be a promising switch device for beyond 30 nm STT-MRAM.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.6
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• pp.300-304
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• 2004

We have proposed the junction termination design employing shallow trench filled with silicon dioxide and field limiting ring (FLR). We have designed trenches between P+ FLRs to decrease the junction termination radius without sacrificing the breakdown voltage characteristics. We have successfully fabricated and measured improved breakdown voltage characteristics of the Proposed device for 1200 V-class applications. The junction termination radius of the proposed device has decreased by 15%-21% compared with that of the conventional FLR at the identical breakdown voltage. The junction termination area of the proposed device has decreased by 37.5% compared with that of the conventional FLR. The breakdown voltage of the proposed device employing 7 trenches was 1156 V, which was 80% of the ideal parallel-plane .junction breakdown voltage.

• Journal of Sensor Science and Technology
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• v.20 no.4
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• pp.230-233
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• 2011

In this paper, highly-efficient optical gating in a junction device based on vanadium dioxide($VO_2$) thin film grown by a sol-gel method was investigated as a gate terminal of a three-terminal device using infrared light with a wavelength of ~1554.6 nm. Due to the photoinduced phase transition, the threshold voltage of the $VO_2$ junction device, at which the device current abruptly jumps, could be tuned with a sensitivity of ~96.5 V/W by adjusting the optical power of the infrared light directly illuminating the device. Compared with the tuning efficiency of the previous device fabricated using $VO_2$ thin film deposited by a pulsed laser deposition method, the threshold voltage of this device could be tuned by ~76.8 % at an illumination power of ~39.8 mW resulting in a tuning efficiency of ~1.930 %/mW, which is ~4.9 times larger than the previous device.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.385-385
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• 2012

A two terminal N+/P/N+ junction device to replace the conventional selective transistor was studied as a bilateral switching device for spin transfer torque (STT) MRAM based on 3D device simulation. An N+/P/N+ junction structure with $30{\times}30nm$ area requires bi-directional current flow enough to write a data by a drain induced barrier lowering (DIBL) under a reverse bias at N+/P (or P/N+ junction), and high current on/off ratio of 106. The SiGe materials are widely used in hetero-junction bipolar transistors, bipolar compensation metal-oxide semiconductors (BiCMOS) since the band gap of SiGe materials can be controlled by changing the fraction and the strain epilayers, and the drift mobility is increased with the increasing Ge content. In this work, N+/P/N+ SiGe material based junction provides that drive current is increased from 40 to $130{\mu}A$ by increased Ge content from 10~80%. When Ge content is about 20%, the drive current density of SiGe device substantially increased to 2~3 times better than Si-based junction device in case of 28 nm P length, which is sufficient current to operation of STT-MRAM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.30.2-30.2
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• 2010

Nano-scale p-n junction can generate various nano-scale functional devices such as nanowire light emitting diode, nanowire solar cell, and nanowire sensor. The core shell type nanowire p-n junction has been considered for the high efficient devices in many previous reports. On the other hand, although device efficiency is relatively lower, the cross bar type p-n junction has simple topological structure, suggested by C.M. Lieber group, to integrate easily many p-n junction devices in one board. In this study, for the integration of the cross bar nanowire p-n junction device, a simple fabrication route, employed dielectrophoretic array and direct printing techniques, was demonstrated by the successful fabrication and programmable integration of the nanowire cross bar p-n junction solar cell. This direct printing process will give the single nanowire solar cell the opportunity of the integration on the circuit board with other nanowire functional devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.286-289
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• 2003

In the case of high voltage devices, junction termination plays an important role in determining the breakdown voltage of the device. The mesa junction termination has been demonstrated to yield nearly ideal breakdown voltage for 6H-SiC p-n junctions. However, such an approach may not be attractive because of the nonplanar surface, which is difficult to passivate. Moreover, In case of 4H-SiC, ideal breakdown voltage could not be achieved using mesa junction termination. For 4H-SiC planar junction termination technique is more useful one rather than mesa junction termination. In this paper, breakdown characteristics of the 4H-SiC device with planar junction termination, such as FLR(Field Limiting Ring), FP(Field Plate) and JTE(Junction Termination Extension), is presented. In the case of the FLR, breakdown voltage of 1800V is obtained. And breakdown voltage of 1000V and 1150V is also obtained for the case of FP and JTE case, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.4
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• pp.270-275
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• 2012

Power MOSFET(metal oxide silicon field effect transistor) operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. But on-resistance characteristics depending on the increasing breakdown voltage spikes is a problem. So 600 V planar power MOSFET compare to 1/3 low on-resistance characteristics of super junction MOSFET structure. In this paper design to 600 V planar MOSFET and super junction MOSFET, then improvement of comparative analysis breakdown voltage and resistance characteristics. As a result, super junction MOSFET improve on about 40% on-state voltage drop performance than planar MOSFET.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.6
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• pp.389-393
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• 2014

A thin metal-embedding Schottky device was fabricated for an efficient photoelectric device. Semitransparent thick of 10 nm metal layers were deposited by sputtering of Ag and Ni on a Si substrate. The (111) N-type Si wafers with one-side polished, 450~500 ${\mu}m$ and resistivity $1{\sim}20{\Omega}{\cdot}cm$ were used. High rectifying ratio about 100 from Ni-Schottky device was achieved. This design would provide an effective scheme for high-performing photoelectric devices.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1409-1418
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• 1990

Characteristics of NMOS transistors with phosphorus source/drain junctions formed by two-step rapid thermal diffusion (RTD) process using a solid diffusion source have been investigated. Phosphorus profiles after RTD were measured by SIMS analysis. In the case of 1100\ulcorner, 10sec RTD of, P, the specific contact resistance of n+ Si-Al was 2.4x10**-7 \ulcorner-cm\ulcorner which is 1/5 of the As junction The comparison fo P junction devices formed by RTD and conventional As junction devices shows that both short channel effect and hot carrier effect of P junction devices are smaller than those of As junction devices when the devices have same junction depths. P junction device had maximum of 0.4 times lower Isub/Id than As junction device. Characteristics of P junction formed by several different RTD conditions have been compared and 1000\ulcorner RTD sample had the smaller hot carrier generation. Also, it has been shown that the hot carrier generation can be futher reduced by forming the P junctions by 3-step RTD which has RTO-driven-in process additionally.