• 제목/요약/키워드: Junction FET

검색결과 29건 처리시간 0.021초

Fabrication of SOI FinFET Devices using Arsenic Solid-phase-diffusion

  • Cho, Won-Ju;Koo, Hyun-Mo;Lee, Woo-Hyun;Koo, Sang-Mo;Chung, Hong-Bay
    • 한국전기전자재료학회논문지
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    • 제20권5호
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    • pp.394-398
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    • 2007
  • A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

비소 고상확산방법을 이용한 MOSFET SOI FinFET 소자 제작 (Fabrication of SOI FinFET devices using Aresnic solid-phase-diffusion)

  • 조원주;구현모;이우현;구상모;정홍배
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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    • pp.133-134
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    • 2006
  • A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

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Partially-insulated MOSFET (PiFET) and Its Application to DRAM Cell Transistor

  • Oh, Chang-Woo;Kim, Sung-Hwan;Yeo, Kyoung-Hwan;Kim, Sung-Min;Kim, Min-Sang;Choe, Jeong-Dong;Kim, Dong-Won;Park, Dong-Gun
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제6권1호
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    • pp.30-37
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    • 2006
  • In this article, we evaluated the structural merits and the validity of a partially insulated MOSFET (PiFET) through the fabrication of prototype transistors and an 80 nm 512M DDR DRAM with partially-insulated cell array transistors (PiCATs). The PiFETs showed the outstanding short channel effect immunity and off-current characteristics over the conventional MOSFET, resulting from self-induced halo region, self-limiting SID shallow junction, and reduced junction area due to PiOX layer formation. The DRAM with PiCATs also showed excellent data retention time. Thus, the PiFET can be a promising alternative for ultimate scaling of planar MOSFET.

Gate-modulated SWCNT/SnO2 nanowire hetero-junction arrays on flexible polyimide substrate

  • 박재현;배민영;하정숙
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2010년도 제39회 하계학술대회 초록집
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    • pp.273-273
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    • 2010
  • Recently, extensive research on hetero-junction arrays has been reported owing to its unique band gaps dissimilar to that of homo-junctions. These hetero-junction devices can be used in laser, solar cells, and various sensors. We report on the facile method to fabricate SWCNTs/SnO2 nanowires hetero-junction arrays on flexible polyimide substrate. Each SWCNT field effect transistor (FET) and SnO2 nanowire FET exhibits the purely p- and n-type charactersistics with ohmic contact properties. Such formed pn-junctions showed rectification behaviors reproducibly with a rectification ratio of ${\sim}3{\times}103$ at 1 V and ideality factors about 12. The pn-junctions also showed a good gate modulation behavior.

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Fabrication of p-type FinFETs with a 20 nm Gate Length using Boron Solid Phase Diffusion Process

  • Cho, Won-Ju
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제6권1호
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    • pp.16-21
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    • 2006
  • A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

20 GHz Push-Push FET 유전체 공진기 발진기 설계 및 실현 (Design and Realization of 20 GHz Push-Push FET Dielectric Resonator Oscillator)

  • 정재권;김인석
    • 한국항행학회논문지
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    • 제6권1호
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    • pp.52-62
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    • 2002
  • 본 논문에서는 출력단에 Wilkinson 전력결합기 또는 T 접합 전력결합기를 사용한 20 GHz Push-Push FET 유전체 공진기 발진기를 설계 제작하고 그 특성을 조사 연구하였다. 기본 주파수 10 GHz를 억제하고 제 2 고조파 주파수를 이용하는 20 GHz Push-Push 발진기를 $TE_{01{\delta}}$ 모드의 유전체 공진기와 GaAs MESFET를 두께 H = 20 mil(${\varepsilon}_r$=2.52) 테프론기판 위에 장착하는 구조로 설계하고 제작하였다. Wilkinson 전력결합기를 이용하여 제작된 발진기는 20 GHz에서 출력 전력이 5.67 dBm, 기본 주파수 억압특성은 -29.33 dBc, 위상 잡음은 100 kHz offset에서 -105.5 dBc/Hz 특성을 나타내었으며, T 접합 전력결합기 이용하여 제작된 발진기는 20 GHz에서 출력 전력이 -1.17 dBm, 기본 주파수 억압특성은 -17.84 dBc, 위상 잡음은 100 kHz offset에서 -102.2 dBc/Hz 특성을 나타내었다.

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Polyvinylidene Fluoride를 게이트 전극으로 이용한 MgO bicrystal Josephson junction의 전기 특성 및 마이크로파 특성 연구 (Electrical Characteristics and Microwave Properties of MgO Bicrystal Josephson Junction with Polyvinylidene Fluoride Gate Electrode)

  • 윤용주;김형민;박광서;김진태
    • Progress in Superconductivity
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    • 제3권1호
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    • pp.74-77
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    • 2001
  • We have fabricated a high-Tc superconductive transistor with polyvinylidene fluoride (PVDF) gate electrode on MgO bicrystal Josephson junction by spin-coating method. The PVDF ferroelectric film is found to be suitable fur a gate electrode of the superconductive transistor since it has not only small leakage current but also high dieletric constant at low temperature. For the application of superconducting-FET, we investigated millimeter wave properties (60 GHz band) of the Josephson junction with PVDF gate electrode.

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K 대역 Push-Push 유전체 공진기 발진기 설계 및 제작 (Design and Fabrication of K Band Push-Push Dielectric Resonator Oscillator)

  • 정재권;박승욱;김인석
    • 한국전자파학회논문지
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    • 제13권7호
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    • pp.613-624
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    • 2002
  • 본 논문에서는 Push-Push FET유전체 공진기 발진기를 20 GHz에서 설계, 제작하고 출력단에 각각 Wilkinson 전력결합기와 T 접합 전력결합기를 사용하였을 때의 각 결합기의 반사손실과 격리도 특성에 따른 발진기의 출력특성을 조사하여 이들 특성이 출력과 위상잡음 특성에 각각 영향을 주는 것을 설명한다. 기본 주파수 10 GHz를 억제하고 제 2고조파 주파수를 이용하는 20 GHz Push-Push발진기는 T $E_{01}$$\delta$/모드의 유전체 공진기와 GaAs MESFET를 높이 H = 20 mil($\varepsilon_{{\gamma}}$/=2.52) 테프론 기판 위에 장착하는 구조로 설계하고 제작하였다. 기본주파수에서 T-접합 전력결합기는 반사손실 -12 dB, 격리도 -3.7 dB 이었고, Wilkinson 전력결합기는 반사손실 -14 dB, 격리도 -11 dB 이었다. 그리고 제 2 고조파 주파수에서 T-접합 전력결합기는 반사손실 -10 dB, 격리도 -7.5 dB 이었고, Wilkinson 전력 결합기 는 반사손실 -23 dB, 격리도 -22 dB를 보였다. 결과적으로 반사손실과 격리도 특성이 좋은 Wilkinson 전력 결합기를 출력 단으로 이용한 Push-Push 발진기 가 출력전력레벨면이나 위상잡음특성면에서 T-접합 전력결합기를 이용한 발진기보다 우수한 특성을 보이는 것을 확인하였다.발진기보다 우수한 특성을 보이는 것을 확인하였다.

The Electrical Characteristics of Power FET using Super Junction for Advance Power Modules

  • Kang, Ey Goo
    • 전기전자학회논문지
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    • 제17권3호
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    • pp.360-364
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    • 2013
  • The maximum breakdown voltage's characteristic within the Super Junction MOSFET structure comes from N-Drift and P-Pillar's charge balance. By developing P-Pillar from Planar MOSFET, it was confirmed that the breakdown voltage is improved through charge balance, and by setting the gate voltage at 10V, the characteristic comparisons of Planar MOSFET and Super Junction MOSFET are shown in picture 6. The results show that it had the same breakdown voltage as Planar MOSFET which increased temperature resistance by 87.4% at $.019{\Omega}cm^2$ which shows that by the temperature resistance increasing, the power module's power dissipation improved.