• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.155-160
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• 2023

The potential performance benefits of Silicon Carbide(SiC) MOSFETs in high power, high frequency power switching applications have been well established over the past 20 years. In the past few years, SiC MOSFET offerings have been announced by suppliers as die, discrete, module and system level products. In high-voltage SiC vertical devices, major design concerns is the edge termination and cell pitch design Field Limiting Rings(FLR) based structures are commonly used in the edge termination approaches. This study presents a comprehensive analysis of the impact of variation of FLR and JFET region on the performance of a 3.3 kV SiC MOSFET during. The improvement in MOSFET reverse bias by optimizing the field ring design and its influence on the nominal operating performance is evaluated. And, manufacturability of the optimization of the JFET region of the SiC MOSFET was also examined by investigating full-map electrical characteristics.

• 전자공학회논문지A
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• 제28A권5호
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• pp.370-374
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• 1991

A high performance fully ion-implanted InP JFET was characterized for high speed switching elements. The switch has an insertion loss of 5.5dB with 31.6dB isolation at 1GHz. This device can effectively swithc a byte-multiplexed 2Gb/s signal and an eye-diagram taken at 2Gb/s shows an error-free eye pattern. Therefore, this device can be used as a switching element for high transmission data rate for monolithic integration of optoelectronic circuit in the long-wavelength region.

• 전기의세계
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• 제30권10호
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• pp.645-654
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• 1981

A technique has been proposed for fabricating a submicron channel vertical V-groove JFET using standard photolithography. A finite element numerical simulation of the V-groove JFET operation was performed using a FORTRAN progrma run on a Cyber-174 computer. The numerical simulation predicts pentode like common source output characteristics for the p$^{+}$n Vertical V-groove JFET with maximum transconductance representing approximately 6 precent of the zero bias drain conductance value and markedly high drain conductance at large drain voltages. An increase in the acceptor concentration of the V-groove JFET gate was observed to cause a significant increase in the transconductance of the device. Therefore, as above mentioned, this paper is study on the analysis of a Vertical V-groove Junction Field Effect Transistor with Finite Element Method.d.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2015년도 제46회 하계학술대회
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• pp.1020-1021
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• 2015

본 논문에서는 상용전압 AC 220V를 인가전압으로 사용하여 PMIC(Power Management IC)의 구동에 적합한 전압을 인가해주는 Pre-Regulator를 설계하였다. 설계된 Pre-Regulator는 상용전압을 사용하기 때문에 Device의 내압이 700V인 Magnachip $0.35{\mu}m$ BCD 공정을 이용하여 설계되었으며, 회로의 구성은 저전압 입력 보호 기능 및 JFET의 구동 제어를 위한 Under Voltage Lock Out(UVLO)회로, 전압조정기(Regulator)의 기준전압을 생성해주는 밴드갭 기준전압 발생(Bandgap Reference)회로, LDO(Low Drop Out)회로로 구성되어있다.

• 대한전자공학회논문지SD
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• 제42권1호
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• pp.25-32
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• 2005

본 논문에서는 단 채널 GaAs MESFET과 SOI-구조의 Si JFET가 갖는 전형적인 특성: i) 드레인 전압 인가에 의한 문턱전압 roll-off, ii) 포화영역에서의 유한한 ac 출력저항, iii) 채널길이에 대한 드레인 포화전류의 의존성 약화, 등을 통합적으로 기술할 수 있는 해석적 모델을 제안하였다. 채널 방향의 전계 변화를 포함하는 새로운 형태의 가정을 기존의 GCA와 대체하고, 채널의 전류 연속성과 전계-의존 이동도를 고려하여, 공핍영역과 전도 채널에서 2차원 전위분포 식을 도출해 내었다. 이 결과, 문턱전압, 드레인 전류의 표현 식들이 동작전압전 구간의 영역에 걸쳐 비교적 정확하게 도출되었다. 또한 본 모델은 기존의 채널 shortening 모델에 비해 Early 효과에 대한 보다 더 적절한 설명을 제공하고 있음을 보이고 있다.

• 한국광학회:학술대회논문집
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• 한국광학회 1991년도 제6회 파동 및 레이저 학술발표회 Prodeedings of 6th Conference on Waves and Lasers
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• pp.190-193
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• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.

• 대한전자공학회논문지
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• 제24권5호
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• pp.794-803
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• 1987

In this paper, the SPICE 2.G6 JFET subroutine and other related subroutines are modified for circuit simulation of GaAs MESFET IC's. The hyperbolic tangent model is used for the drain current-voltage characteristics of GaAs MESFET's and derived channel-conductance and drain-conductance model from the above current model are implemented into small-signal model of GaAs MESFET's. And, device capacitance model which consider after-pinch-off state are modified, and device charge model for SPICE 2G.6 are proposed. The result of modification is shown to be suitable for GaAs circuit simulator, showing good agreement with experimetal results. Forthermore the DC convergence of this paper is better than that of SPICE 2.G JFET subroutine. GaAs MESFET model in this paper is applied for both depletion mode GaAs MESFET and enhancement-mode GaAs MESFET without difficulty.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.63-63
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• 2009

In this work, we demonstrate 800V 4H-SiC power DMOSFETs with several structural alterations to observe static DC characteristics, such as a threshold voltage ($V_{TH}$) and a figure of merit ($V_B^2/R_{SP,ON}$). To optimize the static DC characteristics, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. Design parameters are optimized using 2D numerical simulations and the 4H-SiC DMOSFET structure results in high figure of merit ($V_B^2/R_{SP,ON}$>~$340MW/cm^2$) for a power MOSFET in $V_B{\sim}1200V$ range.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.350-350
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• 2010

Silicon carbide (SiC), one of the well known wide band gap semiconductors, shows high thermal conductivities, chemical inertness and breakdown energies. The design of normally-off 4H-SiC VJFETs [1] has been reported and 4H-SiC VJFETs with different lateral JFET channel opening dimensions have been studied [2]. In this work, 4H-SiC based VJFETs has been designed using the device simulator (ATLAS, Silvaco Data System, Inc). We varied the n-epi layer thickness (from $6\;{\mu}m$ to $10\;{\mu}m$) and the channel width (from $0.9\;{\mu}m$ to $1.2\;{\mu}m$), and investigated the static characteristics as blocking voltages, threshold voltages, on-resistances. We have shown that silicon carbide JFET structures of highly intensified blocking voltages with optimized figures of merit can thus be achieved by adjusting the epi layer thickness and channel width.

• 한국전기전자재료학회논문지
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• 제22권8호
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• pp.637-640
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• 2009

In this work, we demonstrate 800 V 4H-SiC power DMOSFETs with several structural alterations to obtain a low threshold voltage ($V_{TH}$) and a high figure of merit ($V_B\;^2/R_{SP,ON}$), To optimize the device performance, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. These parameters are optimized using 2D numerical simulation and the 4H-SiC DMOSFET structure results in a threshold voltage ($V_{TH}$) below $^{\sim}$3.8 V, and high figure of merit ($V_B\;^2/R_{SP,ON}$>$^{\sim}$200 $MW/cm^2$) for a power MOSFET in $V_B\;^{\sim}$800 V range.