• Journal of Animal Science and Technology
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• v.48 no.3
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• pp.467-478
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• 2006

Maintenance of an optimal air quality in the enclosed pig building is potentially important in terms of pig performance and farmer health. The objective of this on-site experiment is to evaluate and compare efficiencies of currently utilized biological additives to reduce odor emissions from the enclosed pig building. As a result, generally all the additives except for salt water, artificial spice and essential oil were proved ineffective in reducing odor generation. The beneficial effects of salt water, artificial spice and essential oil on odor reduction were highlighted on ammonia, odor intensity and offensiveness, and sulfuric odorous compounds, respectively. To efficiently utilize odor masking agent such as the artificial spice, ventilation rate should keep slightly lower than the optimal level. Essential oil functioned well as not only masking agent but also antimicrobial agent for reducing odor. To precisely quantify odor concentration, it should be measured by not the odor sensor but the olfactometry technique.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.420-424
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• 1999

In this paper, an optical switching circuit and several types of all-optical transmitter/receiver circuits which are configured with photodiodes, multiple quantum-well(MQW) optical modulators, and field-effect transistors(FETs) were simulated using PSPICE and their results of these are examined and discussed. 20 $\mu\textrm{m}$ ${\times}$ 20 $\mu\textrm{m}$ of window size was used for the optical modulators and 100 $\mu\textrm{m}$ wide FETs with the transconductance value of 55 mS/mm were used for the simulations. Simulation results clearly show that in order for the high speed operation of the all-optical circuits, the size of each device should be minimized to reduce the parasitic capacitance, the circuits should be designed to operate at the wavelength where the resposivity of photodiodes becomes the maximum peak, and the use of short, high-intensity input optical signal beams is very advantageous.

• Journal of Sensor Science and Technology
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• v.23 no.4
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• pp.284-289
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• 2014

In this paper, modeling of a gate/body-tied (GBT) PMOSFET photodetector with built-in transfer gate is performed. It can control the photocurrent with a high-sensitivity. The GBT photodetector is a hybrid device consisted of a MOSFET, a lateral BJT, and a vertical BJT. This device allows for amplifying the photocurrent gain by $10^3$ due to the GBT structure. However, the operating parameters of this photodetector, including its photocurrent and transfer characteristics, were not known because modeling has not yet been performed. The sophisticated model of GBT photodetector using a process simulator is not compatible with circuit simulator. For this reason, we have performed SPICE modeling of the photodetector with reduced complexity using Cadence's Spectre program. The proposed modeling has been demonstrated by measuring fabricated chip by using 0.35 im 2-poly 4-metal standard CMOS technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.145-150
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• 1998

8$\times$8 bit scaled SONOSFET NAND type flash EEPROM that shows better characteristics on cell density and endurance than NOR type have been designed and its electrical characteristics are verified with computer aided simulation. For the simulation, the spice model parameter was extracted from the sealed down SONOSFET that was fabricated by $1.5mutextrm{m}$ topological design rule. To improve the endurance of the device, the EEPROM design to have modified Fowler-Nordheim tunneling through the whole channel area in Write/Erase operation. As a result, it operates Write/Erase operation at low current, and has been proven Its good endurance. The NAND type flash EEPROM, which has upper limit of V$_{th}$, has the upper limit of V$_{th}$ as 4.5V. It is better than that of floating gate as 4V. And a EEPROM using the SONOSFET without scaling (65$\AA$-l65$\AA$-35$\AA$), was also designed and its characteristics have been compared. It has more possibliity of error from the V$_{th}$ upper limit as 4V, and takes more time for Read operation due to low current. As a consequence, it is proven that scaled down SONOSFET is more pertinent than existing floating gate or SONOSFET without scaling for the NAND type flash EEPROM.EPROM.

• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.1
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• pp.24-29
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• 2006

A new oscillatory neural circuit with computational function has been designed and been designed and fabricated in an $0.5{\mu}m$ double poly CMOS technology. The proposed oscillatory circuit consists of 3 neural oscillators with excitatory synapses and a neural oscillator with inhibitory synapse. The oscillator block which is a basic element of the neural circuit is designed with a variable negative resistor and 2 transconductors. The variable negative resistor which is used as a input stage of the oscillator consist of a bump circuit with Gaussian-like I-V curve. SPICE simulations of a designed neural circuit demonstrate cooperative computation. Measurements of the fabricated neural chip in condition of ${\pm}$ 2.5 V power supply are shown and compared with the simulated results.

• Journal of the Korean Society for Railway
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• v.15 no.2
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• pp.116-121
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• 2012

DC/DC switching power converters produce DC output voltages from different DC input sources. The converter is used in regenerative braking of DC motors to return energy back in the supply, resulting in energy savings for the systems containing frequent stops. The DC/DC converter is composed of a PWM-IC (pulse width modulation integrated circuit) controller, a MOSFET (metal-oxide semi-conductor field-effect transistor), an inductor, capacitors, and resistors, etc. PWM is applied to control and regulate the total output voltage. In this paper, radiation shows the main influence on the changes in the electrical characteristics of comparator, operational amplifier, etc. in PWM-IC. In the PWM-IC operation, the missing pulses, the changes in pulse width, and the changes of the output waveform are studied by the simulation program with integrated circuit emphasis (SPICE) and compared with experiments.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.128-131
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• 2003

The number of grain is determined based on Poisson distribution in respectively different active channel and it is converted to grain size which affects to the mobility and threshold voltage. the acquired data is applied to the SPICE for observing the variation of I-V characteristic with several channel lengths. we can confirm the effect on device.

• Journal of IKEEE
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• v.23 no.3
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• pp.878-882
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• 2019

XOR(exclusive-OR)-XNOR(exclusive NOR) circuit is a basic component of 4-2 compressor for high performance arithmetic operation. In this paper we propose an energy efficient XOR-XNOR circuit. The proposed circuit is reduced the internal parasitic capacitance in critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit has a 14.5% reduction in propagation delay time and a 1.7% increase in power consumption. Therefore, the proposed XOR-XNOR is reduced power-delay- product (PDP) by 13.1% and energy-delay-product (EDP) by 26.0%. The proposed circuits are implemented with standard CMOS 0.18um technology and verified through SPICE simulation with 1.8V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.65-72
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• 2013

This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Memristor-CMOS and is verified with SPICE-like Memristor model under $0.18{\mu}m$ CMOS technology. As a result, an example design Memristor-CMOS full adder has only 47.6 % of silicon area compare to the CMOS full-adder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.20-28
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• 2006

A new TWA(Traveling-wave-based Waveform Approximation)-based signal integrity verification method for practical interconnect layout structures which are composed of non-uniform RLC lines with various discontinuities is presented. Transforming the non-uniform lines into virtual uniform lines, signal integrity of the practical layout structures can be very efficiently estimated by using the TWA-technique. It is shown that the proposed technique can estimate the signal integrity much more efficiently than generic SPICE circuit model with 5% timing error and 10% crosstalk error.