• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.104-110
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• 2011

A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.308-314
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• 2006

A line scan camera is applied to enhance COG(Chip On Glass) inspection accuracy to be measured a few micro unit. The foreign substance detection among various faulty factors has been the most difficult technology in the faulty automatic inspection step since COG pattern is very miniature and complexity. In this paper, we proposed two step area segmentation template matching method to increase matching speed. Futhermore to detect foreign substance(such as dust, scratch) with a few micro unit, the new method using gradient mask and AND operation was proposed. The proposed 2 step template matching method increased 0.3 - 0.4 second matching speed compared with conventional correlation coefficient. Also, the proposed foreign substance applied masks enhanced $5-8\%$ faulty detection rate compared with conventional no mask application method.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.10
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• pp.112-118
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• 2021

In this study, an inspection method using a color image is proposed to conduct a real-time inspection of covalent organic framework (COF) films to detect defects, if any. The COF film consists of an upper pattern SR and a lower PI. The proposed system detects the defects of more than 20 ㎛ on the SR surface owing to the characteristics of the pattern, whereas on the PI surface, it detects defects of more than 4 ㎛ by utilizing a micro-optical system. In the existing system, it is difficult for the operator to conduct a full inspection through a high-performance microscope. The proposed inspection algorithm performs the inspection by separating each color component using the color contrast of the pattern on the SR side, and on the PI surface it inspects the bonding state of the mounted chip. As a result, it is possible to confirm the exact location of the defects through the SR and PI surface inspections in the implemented inspection.

• Korean Journal of Remote Sensing
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• v.36 no.5_2
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• pp.867-879
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• 2020

As the era of space technology utilization is approaching, the launch of CAS (Compact Advanced Satellite) 500-1/2 satellites is scheduled during 2021 for acquisition of high-resolution images. Accordingly, the increase of image usability and processing efficiency has been emphasized as key design concepts of the CAS 500-1/2 ground station. In this regard, "CAS 500-1/2 Image Acquisition and Utilization Technology Development" project has been carried out to develop core technologies and processing systems for CAS 500-1/2 data collecting, processing, managing and distributing. In this paper, we introduce the results of the above project. We developed an operation system to generate precision images automatically with GCP (Ground Control Point) chip DB (Database) and DEM (Digital Elevation Model) DB over the entire Korean peninsula. We also developed the system to produce ortho-rectified images indexed to 1:5,000 map grids, and hence set a foundation for ARD (Analysis Ready Data)system. In addition, we linked various application software to the operation system and systematically produce mosaic images, DSM (Digital Surface Model)/DTM (Digital Terrain Model), spatial feature thematic map, and change detection thematic map. The major contribution of the developed system and technologies includes that precision images are to be automatically generated using GCP chip DB for the first time in Korea and the various utilization product technologies incorporated into the operation system of a satellite ground station. The developed operation system has been installed on Korea Land Observation Satellite Information Center of the NGII (National Geographic Information Institute). We expect the system to contribute greatly to the center's work and provide a standard for future ground station systems of earth observation satellites.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.8-14
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• 2012

Improving the speed of image processing is in great demand according to spread of high quality visual media or massive image applications such as 3D TV or movies, AR(Augmented reality). SIMD computer attached to a host computer can accelerate various image processing and massive data operations. MAMS is a multi-access memory system which is, along with multiple processing elements(PEs), adequate for establishing a high performance pipelined SIMD machine. MAMS supports simultaneous access to pq data elements within a horizontal, a vertical, or a block subarray with a constant interval in an arbitrary position in an $M{\times}N$ array of data elements, where the number of memory modules(MMs), m, is a prime number greater than pq. MAMS-PP4 is the first realization of the MAMS architecture, which consists of four PEs in a single chip and five MMs. This paper presents implementation of image processing algorithms and performance analysis for MAMS-PP16 which consists of 16 PEs with 17 MMs in an extension or the prior work, MAMS-PP4. The newly designed MAMS-PP16 has a 64 bit instruction format and application specific instruction set. The author develops a simulator of the MAMS-PP16 system, which implemented algorithms can be executed on. Performance analysis has done with this simulator executing implemented algorithms of processing images. The result of performance analysis verifies consistent response of MAMS-PP16 through the pyramid operation in image processing algorithms comparing with a Pentium-based serial processor. Executing the pyramid operation in MAMS-PP16 results in consistent response of processing time while randomly response time in a serial processor.

• Korean Journal of Remote Sensing
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• v.37 no.3
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• pp.431-447
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• 2021

Recently, the use of high-resolution satellites is increasing in many areas. In order to supply useful satellite images stably, it is necessary to establish automatic precision geometric correction technic. Geometric correction is the process that corrected geometric errors of satellite imagery based on the GCP (Ground Control Point), which is correspondence point between accurate ground coordinates and image coordinates. Therefore, in the automatic geometric correction process, it is the key to acquire high-quality GCPs automatically. In this paper, we proposed iterative precision geometry correction method. we constructed an image pyramid and repeatedly performed GCP chip matching, outlier detection, and precision sensor modeling in each layer of the image pyramid. Through this method, we were able to acquire high-quality GCPs automatically. we then improved the performance of geometric correction of high-resolution satellite images. To analyze the performance of the proposed method, we used KOMPSAT-3 and 3A Level 1R 8 scenes. As a result of the experiment, the proposed method showed the geometric correction accuracy of 1.5 pixels on average and a maximum of 2 pixels.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.69-72
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• 2000

This paper shows the more improved design of MRI receiver compared to conventional one based on Elscint Spectrometer. At first, the low-cost ADC is 16 bits, 3MHz sampling A/D converter Comparing to conventional one with signal bits of 14 bits, this device with those of 16 bits helps getting Improved the image resolution improved. If frequency is designed centering around 7.6 MHz to be satisfied in 10 MHz of maximum input bandwidth of ADC. For 1st demodulation, fixed IF is used for the purpose of the implementing multi nuclei system. Control parts & partial digital parts are integrated on one chip(FPGA). In DDC(Digital Down Converter), we got required bandwidth of LPF by controlling its decimation rate. With above considerations, we designed optimal receiver for high resolution imaging to be implemented through PC interface & experimental test of receiver of MRI after receiver's fabrication.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2645-2648
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• 2003

In this paper, real-time and reconfiguable hardware filter for face recognition is proposed and implemented on FPGA chip using verilog-HDL. In general, face recognition is considerably difficult because it is influenced by noises or the variation of illumination. Some of the commonly used filters such s histogram equalization filter, contrast stretching filter for image enhancement and illumination compensation filter are proposed for realizing more effective illumination compensation. The filter proposed in this paper was designed and verified by debugging and simulating on hardware. Experimental results show that the proposed filter system can generate selective set of real-time reconfiguable hardware filters suitable for face recognition in various situation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.127-138
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• 2012

In this paper, we propose a real-time virtual re-convergence hardware platform especially to reduce the visual fatigue caused by stereoscopy. Our unique idea to reduce visual fatigue is to utilize the virtual re-convergence based on the optimized disparity-map that contains more depth information in the negative disparity area than in the positive area. Our virtual re-convergence hardware platform, which consists of image rectification, disparity estimation, depth post-processing, and virtual view control, is realized in real time with 60 fps on a single Xilinx Virtex-5 FPGA chip.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.134-137
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• 2008

This paper proposes a novel quadrature VCO(QVCO) based on direct back-gate second harmonic coupling. The QVCO directly couples the current sources of the conventional LC VCOs through the back-gate instead of front-gate to generate quadrature signals. By the second harmonic injection locking, the two LC VCOs can generate quadrature signals without using on-chip transformer, or stability problem that is inherent in the direct front-gate second harmonic coupling. The proposed QVCO is implemented in $0.18{\mu}m$ CMOS technology operating at 2 GHz with 5.0 mA core current consumption from 1.8 V power supply. The measured phase noise of the proposed QVCO is - 63 dBc/Hz at 10 kHz offset, -95 dBc/Hz at 100 kHz offset, and -116 dBc/Hz at 1 MHz offset from the 2 GHz output frequency, respectively. The calculated figure of merit(FOM) is about -174 dBc/Hz at 1 MHz offset. The measured image band rejection is 46 dB which corresponds to the phase error of $0.6^{\circ}$.