• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.728-734
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• 2001

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects at system speed. Experimental design shows that the technique proposed requires much less area than a commercial approach.

• ETRI Journal
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• v.30 no.3
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• pp.403-411
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• 2008

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.13-21
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• 2010

IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.109-118
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• 2007

As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.77-86
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• 2010

This paper presents an efficient secure scan design technique which is based on a fake key and IEEE 1149.1 instruction to protect secret key from scan-based side channel attack for an Advanced Encryption Standard (AES) core embedded on an System-on-a-Chip (SoC). Our proposed secure scan design technique can be applied to crypto IP core which is optimized for applications without the IP core modification. The IEEE 1149.1 standard is kept, and low area, low power consumption, very robust secret-key protection and high fault coverage can be achieved compared to the existing methods.

• Annual Conference of KIPS
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• 2002.04b
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• pp.1619-1622
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• 2002

최근에 생산되는 디지털 VLSI칩들은 그 집적도가 계속 높아지고 있으며, 이러한 칩들을 장착한 보드의 경우도 그 복잡성이 점차 높아지고 있다. 이에 따라 칩 및 보드에 대한 철저한 테스트 과정이 요구된다. 지금까지 보드 테스트 방법으로 널리 쓰였던 ICT(In-Circuit Test)는 칩의 고집적화에 따른 핀 간격의 조밀화와 SMT(Surface Mount Technology), BGA(Ball Grid Array), MCM(Multi Chip Module) 등의 새로운 패키징 방식의 등장에 따라 테스트 방법으로의 한계성을 드러내고 있다. 이에 대한 대안으로 등장한 IEEE Std 1149.1 은 ICT의 한계성을 극복할 수 있는 기술일 뿐 아니라 여러 가지 장점을 가지고 있으며 그 활용 분야도 다양하다. 본 논문에서는 IEEE Std 1149.1에 따라 설계된 보드 상에서 발생 가능한 고장들에 대한 고장 모델을 제시한다. 또한 각 고장 모델들의 양상과 진단 기법을 제시한다. 이를 통해 IEEE Std 1149.1에 따라 설계된 보드 상에서 발생한 고장들을 검출할 수 있으며, 고장의 종류 및 성격, 그리고 고장의 발생 위치 등의 정보를 얻을 수 있다. IEEE Std 1149.1에 따른 보드 설계가 보드의 신뢰성 보장에 긴요함을 인식하는 계기가 되기를 기대하며 제시된 고장 모델 및 진단 기법이 기술적으로 중요한 참고자료가 되기를 기대한다.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.10-21
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• 1998

In this paper, we analyze the problems of conventional and previous mehtod on delay test method in IEEE 1149.1. To solve them, we propose two kinds of delay test architectures. One is called ARCH-C, is for combinatonal circuit, and the other is ARCH-S, for clocked sequential circuit. ARCH-C is able to detect delay defect of 0.5 $T_{tck}$ or 1 $T_{tck}$ size. And ARCH-C have a fixed and small amount of hardware overhead, on the contrary preious method has a hardware overhead on the dependent of CUT. This paper discusses weveral problems of Delay test on IEEE 1149.1 for clocked sequential circuit. We suggest the method called ARCH-S, is based on a clock counting technique to generate continuous clocked input of CUT. the simulation results ascertain the accurate operation and effectiveness of the proposed architectures.res.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10c
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• pp.662-664
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• 1998

IEEE 1149.1 바운다리스캔은 보드 수준에서 고장점검 및 진단을 위한 테스트 설계기술이다. 그러나, 바운다리스캔 제어기의 특성상 테스트 패턴의 주입에서 관측까지 2.5 TCK가 소요되므로, 연결선상의 지연고장을 점검할 수 없다. 본 논문에서는 Update_DR 신호를 변경하여, 테스트 패턴 주입에서 관측까지 1 TCK가 소요되게 함으로써, 지연고장 점검을 가능하게 하는 기술을 소개한다. 나아가서, 정적인 고장점검을 위한 테스트 패턴을 개선해 지연고장 점검까지 가능하게 하는, N개의 net에 대한 2log(N+2)의 새로운 테스트패턴도 제안한다. 설계와 시뮬레이션을 통해 지연고장 점검이 가능함을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.61-71
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• 2003

Interconnect test for highly integrated environments like SoC, becomes more important as the complexity of a circuit increases. This importance is from two facts, test time and complete diagnosis. Since the interconnect test between IPs is based on the scan technology such as IEEE1149.1 and IEEE P1500, it takes long test time to apply test vectors serially through a long scan chain. Complete diagnosis is another important issue because a defect on interconnects are shown as a defect on a chip. But generally, interconnect test algorithms that need the short test time can not do complete diagnosis and algorithms that perform complete diagnosis need long test time. A new interconnect test algorithm is developed. The new algorithm can provide a complete diagnosis for all faults with shorter test length compared to the previous algorithms.