Journal of the Korean Institute of Telematics and Electronics C (전자공학회논문지C)
- Volume 35C Issue 2
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- Pages.10-21
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- 1998
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- 1226-5853(pISSN)
Delay test for combinational and sequential circuit on IEEE 1149.1
조합회로와 순서회로를 위한 경계면 스캔 구조에서의 지연시험
Abstract
In this paper, we analyze the problems of conventional and previous mehtod on delay test method in IEEE 1149.1. To solve them, we propose two kinds of delay test architectures. One is called ARCH-C, is for combinatonal circuit, and the other is ARCH-S, for clocked sequential circuit. ARCH-C is able to detect delay defect of 0.5
Keywords