• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.9
• /
• pp.6247-6253
• /
• 2015

This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix $0.18{\mu}m$ CMOS parameters. Chip layout size is $500{\mu}m{\times}150{\mu}m$. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.7
• /
• pp.1227-1234
• /
• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.310-310
• /
• 2012

최근 전자산업의 발달에 따른 전자제품의 소형화 및 고기능화 요구에 대응하기 위하여 저항(resistor), 커패시터(capacitor), IC (integrated circuit) 등의 수동소자를 개별 칩(discrete chip) 형태로 형성하여 기판의 표면에 실장하는 기술이 일반화되고 있다. 그러나, 수동 소자의 내장 기술은 기판의 패턴 밀도의 급격한 향상과 더불어 수동소자의 내장 공간도 협소해지는 문제점이 있다. 상기의 문제점을 해결하기 위해 개별 칩 형태의 내장형 저항체를 박막 형태의 내장 저항체를 구현하는 기술의 개발이 최근 주목을 받고 있다. 박막 저항체는 기존의 권선저항 및 후막저항과 비교하여 정밀한 온도저항계수를 가지며 이동통신에 적용시 고주파 영역(GHz)에서의 안정성과 주파수 특성이 좋다는 장점들을 가지고 있다. 박막 저항 물질로는 높은 경도와 우수한 열적 안정성을 가지고 있는 TaN (tantalum nitride)이 주로 사용되고 있다. 일반적으로, TaN 박막은 스퍼터링을 사용하며 제조되며 TaN 박막의 성질은 탄탈륨과 질소의 화학정량비, 박막의 결함 정도, 또는 공정압력 및 증착 온도, 플라즈마 파워 등과 같은 공정조건 등의 변화에 민감하게 변화하므로, TaN 박막의 다양한 연구가 더 필요한 실정이다. 본 연구에서는 반응성 마크네트론 스퍼터링을 사용하여 TaN 박막을 Si 기판 위에 증착하였고 TaN 박막의 원하는 특성을 제어할 수 있도록 질소 분압과 total gas volume을 조절하여 공정을 최적화하는 연구를 진행하였다. 또한 tensile pull-off 방법을 이용하여 TaN 박막의 부착강도를 평가하였고, 온도 사이클 및 고온고습 환경에 노출된 TaN 박막들의 열화 특성들에 대하여 연구하였다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.4
• /
• pp.216-231
• /
• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.9
• /
• pp.68-73
• /
• 2009

This paper presents an easily modifiable structure of a serial peripheral interface (SPI) that is suitable for efficient testing of CMOS RF integrated circuits. The proposed SPI Is designed so that the address size and the accompanying software can be easily adjusted and modified according to the requirements and complexity of RF IC's under development. The hardware architecture and software algorithm to achieve the flexibility are described. The proposed SPI is fabricated in $0.13{\mu}m$ CMOS and successfully verified experimentally with a 2.7GHz fractional-N delta-sigma frequency synthesizer as a device under test.

• Journal of Dental Anesthesia and Pain Medicine
• /
• v.20 no.2
• /
• pp.73-81
• /
• 2020

Background: The international organization for standardization (ISO) 80601-2-61 dictates that the accuracy of a pulse oximeter should be assessed by a controlled desaturation study. We aimed to characterize the relationship between the fraction of inspired oxygen (FiO₂) and peripheral oxygen saturation (SpO₂) using a turnover model by retrospectively analyzing the data obtained from previous controlled desaturation studies. Materials and Methods: Each volunteer was placed in a semi-Fowler's position and connected to a breathing circuit to administer the hypoxic gas mixture containing medical air, oxygen, nitrogen, and carbon dioxide. Volunteers were exposed to various levels of induced hypoxia over 70-100% arterial oxygen saturation (SaO₂). The study period consisted of two rounds of hypoxia and the volunteers were maintained in room air between each round. FiO₂ and SpO₂ were recorded continuously during the study period. A population pharmacodynamic analysis was performed with the NONMEM VII level 4 (ICON Development Solutions, Ellicott City, MD, USA). Results: In total, 2899 SpO₂ data points obtained from 20 volunteers were used to determine the pharmacodynamic characteristics. The pharmacodynamic parameters were as follows: k_out = 0.942 1/min, Imax = 0.802, IC₅₀ = 85.3%, γ = 27.3. Conclusion: The changes in SpO₂ due to decreases in FiO₂ well explained by the turnover model with inhibitory function as a sigmoidal model.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.6
• /
• pp.610-616
• /
• 2010

In this paper, particle swarm optimization(PSO) is applied for the design of frequency selective surface based artificial magnetic conductor. An equivalent circuit model for this artificial magnetic conductor(AMC) with Jerusalem Cross arrays was derived and then PSO was applied for obtaining the optimized geometrical parameters with desired resonant frequency. The resonant frequency and the reflection phase characteristics from the optimization were compared to the results from commercial software for verifying the validity of this paper. The procedure presented in this paper can be applied to design the AMC with different frequency selective surface and also can be used for the design of microwave circuits like the AMC ground planes.

• Journal of Sensor Science and Technology
• /
• v.27 no.2
• /
• pp.93-98
• /
• 2018

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

• Proceedings of the KIEE Conference
• /
• 2008.10b
• /
• pp.515-517
• /
• 2008

현재 가동 중인 원자적발전소 계측제어설비의 전원공급기를 살펴보면 인버터 또는 별도의 교류를 입력전원으로 사용한다. 직류 전원공급기들은 설비의 중요도예 따라 이중화로 구성된 설비도 있고 그렇지 않은 기기나 설비도 있다. 이중화로 구성된 전원공급기라 해도 교류 입력전원이 동일하다면 교류 입력이 상실될 때 이중화로 구성된 직류전원도 상실되어 관련계통의 가동이 정지된다. 이러한 문제점을 해결하기 위해서는 각기 다른 교류입력전원으로 동작되는 이중화전원공급기로 구성되는 것이 가장 바람직하다. 본 연구개발의 목적은 두 종의 설비에 소요되는 3종의 직류전원 공급기를 원자력 안정성등급으로 국산화하는 연구이다. 기존 제품들은 3종 모두 리니어 방식의 제품이지만, 방사선감시 계통 현장제어기의 5V로직 전원공급기와 공정제어계통 전원공급자는 전력변환효율이 높고 소형, 정량화가 가능한 SMPS(Switched Mode Power Supply) 방식으로 개발하였다. 방사선감시계통 현장제어기의 PCA(Printed Circuit Assembly) 저전압공급기는 다양한 종류의 출력전압과 저 전류형이므로 안정성 면에서 동일한 형식의 리니어 방식으로 개발하였으며 3종류 모두 출력용량을 20% 이상 향상시켰다. 또한, 논문을 통해 SMPS 방식의 전원공급기의 핵심 부품인 Control Module을 Hybrid IC형으로 자체 설계하여 성능이 우수한 제품을 지속적으로 생산할 수 있는 기틀을 마련하고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.3
• /
• pp.567-574
• /
• 2015

In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.