• Title/Summary/Keyword: Hot carrier

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Effect of Hot Carrier Stress on The Power Performance Degradation in SOI MOSFET (Hot Carrier Stress로 인한 SOI MOSFET의 전력 성능 저하)

  • Lee, Byung-Jin;Park, Sung-Wook;Park, Jong-Kwan
    • 전자공학회논문지 IE
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    • v.45 no.4
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    • pp.7-10
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    • 2008
  • In this work investigates hot carrier stress on the RF power of SOI MOSFET using load-pull measurement. We found that the RF power characteristics are affected by the hot carrier stress, and the DC performance of SOI MOSFET is clearly degraded after hot carrier stress at constant voltage measurement. And these experimental observations can be explained by the change of DC performance degradation coefficient under hot carrier stress.

PMOSFET Hot Carrier Lifetime Dominated by Hot Hole Injection and Enhanced PMOSFET Degradation than NMOSFET in Nano-Scale CMOSFET Technology (PMOSFET에서 Hot Carrier Lifetime은 Hole injection에 의해 지배적이며, Nano-Scale CMOSFET에서의 NMOSFET에 비해 강화된 PMOSFET 열화 관찰)

  • 나준희;최서윤;김용구;이희덕
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.7
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    • pp.21-29
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    • 2004
  • Hot carrier degradation characteristics of Nano-scale CMOSFETs with dual gate oxide have been analyzed in depth. It is shown that, PMOSFET lifetime dominate the device lifetime than NMOSFET In Nano-scale CMOSFETs, that is, PMOSFET lifetime under CHC (Channel Hot Carrier) stress is much lower than NMOSFET lifetime under DAHC (Dram Avalanche Hot Carrier) stress. (In case of thin MOSFET, CHC stress showed severe degradation than DAHC for PMOSFET and DAHC than CHC for NMOSFET as well known.) Therefore, the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor in upcoming Nano-scale CMOSFET technology. In case of PMOSFETs, CHC shows enhanced degradation than DAHC regardless of thin and thick PMOSFETs. However, what is important is that hot hole injection rather than hot electron injection play a important role in PMOSFET degradation i.e. threshold voltage increases and saturation drain current decreases due to the hot carrier stresses for both thin and thick PMOSFET. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method. Therefore, suppression of PMOSFET hot carrier degradation or hot hole injection is highly necessary to enhance overall device lifetime or circuit lifetime in Nano-scale CMOSFET technology

A Study on the Channel-Width Dependent Hot-Carrier Degradation of nMOSFET with STI (STI구조를 갖는 nMOSFET의 채널 너비에 따른 Hot-Carrier 열화 현상에 관한 연구)

  • 이성원;신형순
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.9
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    • pp.638-643
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    • 2003
  • Channel width dependence of hot-carrier effect in nMOSFET with shallow trench isolation is analyzed. $I_{sub}$- $V_{G}$ and $\Delta$ $I_{ㅇ}$ measurement data show that MOSFETs with narrow channel-width are more susceptible to the hot-carrier degradation than MOSFETs with wide channel-width. By analysing $I_{sub}$/ $I_{D}$, linear $I_{D}$- $V_{G}$ characteristics, thicker oxide-thickness at the STI edge is identified as the reason for the channel-width dependent hot-carrier degradation. Using the charge-pumping method, $N_{it}$ generation due to the drain avalanche hot-carrier (DAHC) and channel hot-electron (CHE) stress are compared. are compared.

The RF performance degradation in Bulk DTMOS due to Hot Carrier effect (Hot Carrier 현상에 의한 Bulk DTMOS의 RF성능 저하)

  • Park Jang-Woo;Lee Byoung-Jin;Yu Jong-Gun;Park Jong-Tae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.2 s.332
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    • pp.9-14
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    • 2005
  • This paper reports the hot carrier induced RF performance degradation of bulk dynamic threshold voltage MOSFET (B-DTMOS) compared with bulk MOSFET (B-MOS). In the normal and moderate mode operations, the degradations of cut-off frequency $(f_{T})$ and minimum noise figure $(F_{min})$ of B-DTMOS are less significant than those of B-MOS devices. Our experimental results show that the RF performance degradation is more significant than the U performance degradation after hot carrier stressing. Also, the degradation characteristics of RF power Performance of B-DTMOS due to hot carrier effects are measured for the first time.

A study on the hot carrier induced performance degradation of RF NMOSFET′s (Hot carrier에 의한 RF NMOSFET의 성능저하에 관한 연구)

  • 김동욱;유종근;유현규;박종태
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.10
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    • pp.60-66
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    • 1998
  • The hot carrier induced performance degradation of 0.8${\mu}{\textrm}{m}$ RF NMOSFET has been investigated within the general framework of the degradation mechanism. The device degradation model of an unit finger gate MOSFET could be applied for the device degradation of the multi finger gate RF NMOSFET. The reduction of cut-off frequency and maximum frequency can be explained by the transconductance reduction and the drain output conductance increase, which are due to the interface state generation after the hot carrier stressing. From the correlation between hot carrier induced DC and RF performance degradation, we can predict the RF performance degradation just by the DC performance degradation measurement.

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A study hot-carrier degradation on submicron devices (Submicron device에서의 hot-carrier 열화에 관한 연구)

  • 이용희;김현호;최영규;이천희
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.867-870
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    • 1998
  • In this paper we simulated 0.30um NMOS transitor to analysis hot carrier degradation depend on As, As+P, P LDD structure. As a result we obtained As+P LDD structure was good hot carrier immunity. Also we find that hog carrier life time improved a sincresing P dose due to P dose helps in grading the nLDD junction. However As-only junction was poor due to junction high peak position located near the surface.

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A Study on Buffered Deposition Device Structure to Improvement for High Density Chip Realiability (고밀도 칩 신뢰성 개선을 위한 buffered deposition 소자구조에 관한 연구)

  • Kim, Hwan-Seog;Yi, Cheon-Hee
    • Journal of the Korea Society for Simulation
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    • v.17 no.2
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    • pp.13-19
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    • 2008
  • New Buffered deposition is proposed to decrease junction electric field in this paper. Buffered deposition process is fabricated after first gate etch, followed NM1 ion implantation and deposition & etch nitride layer. New Buffered deposition structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of Buffered deposition and conventional. Also, we design a test pattern including NMOSFET, PMOSFET, LvtNMOS, High pressure N/PMOSFET, so that we can evaluate DC/AC hot carrier degradation on-chip. As a result, we obtained 10 years hot carrier life time satisfaction.

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A Study on the Hot-Carrier Effects of p-Channel Poly-Si TFT s (p-채널 Poly-Si TFT s 소자의 Hot-Carrier 효과에 관한 연구)

  • 진교원;박태성;백희원;이진민;조봉희;김영호
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.9
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    • pp.683-686
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    • 1998
  • Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

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Characterization of Hot Carrier Mechanism of Nano-Scale CMOSFETs (나노급 소자의 핫캐리어 특성 분석)

  • Na Jun-Hee;Choi Seo-Yun;Kim Yong-Goo;Lee Hi-Deok
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.327-330
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    • 2004
  • It is shown that the hot carrier degradation due to enhanced hot holes trapping dominates PMOSFETs lifetime both in thin and thick devices. Moreover, it is found that in 0.13 ${\mu}m$ CMOSFET the PMOS lifetime under CHC (Channel Hot Carrier) stress is lower than the NMOSFET lifetime under DAHC (Drain Avalanche Hot Carrier) stress. Therefore. the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method and highly necessary to enhance overall device lifetime or circuit lifetime in upcoming nano-scale CMOS technology.

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GIDL current characteristic in nanowire GAA MOSFETs with different channel Width (채널 폭에 따른 나노와이어 GAA MOSFET의 GIDL 전류 특성)

  • Je, Yeong-ju;Shin, Hyuck;Ji, Jung-hoon;Choi, Jin-hyung;Park, Jong-tae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.889-893
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    • 2015
  • In this work, the characteristics of GIDL current in nanowire GAA MOSFET with different channel width and hot carrier stress. When the gate length is fixed as a 250nm the GIDL current with different channel width of 10nm, 50nm, 80nm, and 130nm have been measured and analyzed. From the measurement, the GIDL is increased as the channel width decreaes. However, the derive current is increased as the channel width increases. From measurement results after hot carrier stress, the variation of GIDL current is increased with decreasing channel width. Finally, the reasons for the increase of GIDL current with decreasing channel width and r device. according to hot carrier stress GIDL's variation shows big change when width and the increase of GIDL current after hot carrier stress are confirmed through the device simulation.

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