• 한국수학교육학회지시리즈A:수학교육
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• 제57권3호
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• pp.311-328
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• 2018

In school mathematics, the concept of an average is not a concept that is limited to a unit of statistics. In particular, high school students will learn about arithmetic mean and geometric mean in the process of learning absolute inequality. In calculus learning, the concept of average is involved when learning the concept of average speed. The arithmetic mean is the same as the procedure used when students mean the test scores. However, the procedure for obtaining the geometric mean differs from the procedure for the arithmetic mean. In addition, if the arithmetic mean and the geometric mean are the discrete quantity, then the mean rate of change or the average speed is different in that it considers continuous quantities. The average concept that students learn in school mathematics differs in the quantitative nature of procedures and objects. Nevertheless, it is not uncommon to find out how students construct various mathematical concepts into mathematical knowledge. This study focuses on this point and conducted the interviews of the students(three) in the second grade of high school. And the expression of students in the process of average concept formation in arithmetic mean, geometric mean, average speed. This study can be meaningful because it suggests practical examples to students about the assertion that various scholars should experience various properties possessed by the average. It is also meaningful that students are able to think about how to construct the mean conceptual properties inherent in terms such as geometric mean and mean speed in arithmetic mean concept through interview data.

• 한국정보통신학회논문지
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• 제17권12호
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• pp.2921-2926
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• 2013

본 논문에서 제안된 십진 부동소수점 연산 장치(decimal floating-point arithmetic unit, DFP)는 L.K.Wang에 의해 제안된 십진 부동소수점 유닛을 기반으로 하여 데이터의 병렬 처리를 통해 동일한 크기의 지수를 갖는 두 오퍼랜드의 가수 영역의 고속 연산을 지원하도록 재설계 하였다. 제안된 십진 부동소수점 연산 장치는 Xilinx ISE를 이용하여 xc2vp30-7ff896 타겟 디바이스로 합성하였으며 (주)시스템센트로이드의 Flowrian을 통해 시뮬레이션 검증하였다. 제안된 방식은 L.K.Wang에 의해 제안된 설계 방식 및 참고문헌 [6]의 설계 방식과 비교하여 동일한 입력 데이터를 이용하여 시뮬레이션 검증한 결과, L.K.Wang 방식보다 약 8.4%, 참고문헌 [6]의 방식보다 약 3% 정도의 처리 속도가 향상되었다.

• 한국수학사학회지
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• 제12권2호
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• pp.47-54
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• 1999

We introduce some historical facts on number theory, especially prime numbers and modular arithmetic. And then, with the viewpoint of computer arithmetic, residue number systems are considered as an alternate to positional number systems so that high performance and high speed computation can be achieved in a specified domain such as cryptography and digital signal processing.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.636-639
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• 2004

In present, there are many methods such as DCT, Wavelet Transform, or Quantization -to the image compression field, but the basic image compression method have based on DCT. The representative thing of the efficient techniques for information compression is DCT method. It is more superior than other information conversion method. It is widely applied in digital signal processing field and MPEG and JPEG which are selected as basis algorithm for an image compression by the international standardization group. It is general that DCT is consisted of using multiplier with main arithmetic blocks having many arithmetic amounts. But, the use of multiplier requires many areas when hardware is embodied, and there is fault that the processing speed is low. In this paper, we designed the hardware module that could run high-speed operation using row-column separation calculation method and Chen algorithm by distributed arithmetic method using ROM table instead of multiplier for design DCT module of high speed.

• ETRI Journal
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• 제30권5호
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• pp.707-717
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• 2008

This paper presents two types of high-speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Area-throughput trade-offs are evaluated depending on the S-box implementation by using look-up tables or combinational logic which involves composite field arithmetic. The sub-pipelined architectures for non-feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S-box implementation using composite field arithmetic over $GF(2^4)^2$, throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 ${\mu}m$ CMOS technology. This is the first sub-pipelined architecture of ARIA for high throughput to date.

• 한국정보통신학회논문지
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• 제21권4호
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• pp.774-780
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• 2017

본 논문은 HEVC의 엔트로피 코딩방법인 CABAC 부호화기를 위한 효율적인 이진 산술 부호화기 하드웨어 구조를 제안한다. CABAC은 HEVC 표준에서 사용되는 엔트로피 코딩 방법으로 통계적 중복성을 제거하여 영상의 높은 압축률을 지원한다. 하지만 이진 산술 부호화(Binary Arithmetic Encode)는 데이터 간의 의존 관계가 높아 병렬처리가 어렵고 실시간 처리의 지연이 발생 된다. 제안하는 이진 산술 부호화기는 입력으로 들어오는 빈을 고속으로 처리하기 위하여 재정규화 과정을 분리 시켜 동작하도록 설계한다. 기존의 반복적인 알고리즘을 병렬적으로 처리함으로써 최대지연시간(Critical Path)을 최적으로 줄일 수 있는 4단계의 파이프라인 구조로 설계하였다. 또한, 멀티-빈 구조를 적용하여 클록 사이클 당 3개의 빈을 처리한다. 제안하는 CABAC의 이진 산술 부호화기는 Verilog-HDL로 설계하였으며 65nm 공정으로 합성하였다. 합성 결과 게이트수는 8.07K 이며 최대 동작주파수는 769MHz로 최대 빈 처리량은 2307Mbin/s이다. 제안하는 하드웨어 구조는 기존의 이진 산술 부호화기와 비교하여 최대 빈 처리량이 26% 만큼 증가 하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1125-1128
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• 1998

A new architecture for high-speed implementation of adaptive decision-feedback equalizer (ADFE) applicable to wide-band digital wireless modems is described. Rather than using conventional two's complement arithmetic, a novel complex-valued filter structure is devised, which is based on redundant binary (RB) arithmetic. The proposed RB complex-valued filter reduces the critical path delay of ADFE, as well as leads to a more compact implementation than conventional methods. Also, the carry-propagation free (CPF) operation of the RB arithmetic enhances its speed. To demonstrate the proposed method, a prototype chip set is designed. They are designed to contain two complexvalued filter taps along with their coefficient updating circuits, and can be cascaded to implement loger filter taps for high bit-rate applications.

• 한국컴퓨터정보학회논문지
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• 제4권4호
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• pp.94-100
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• 1999

본 논문은 흡필드 모델의 실수연산을 고속으로 수행할 수 있는 디지털 신경회로망의 구현에 관한 연구이다. 흡필드 모델［1］-［8］의 연산과정은 행렬-벡터의 연산으로 기술 할 수 있으며, 이 연산과정은 순환, 반복적으로 이루어지므로 어레이프로세서 구조로 설계하기에 적합하다. 또한, Look-up-Table(연산표)에 의하여 비선형 함수를 출력함으로써, 고속의 실수 연산을 수행할 수 있도록 설계하였다. 본 논문에서 제안한 방법은 현재 개발된 VLSI기술로 실현 가능하기 때문에 실제 신경회로망의 응용분야에 이용될 수 있을 것으로 기대된다.

• 대한전자공학회논문지
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• 제25권2호
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• pp.204-210
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• 1988

The residue number system offers the possibility of high-speed operation and error detection/correction because of the separability of arithmetic operations on each digit. A compact residue arithmetic module named the self-checking pulse-train residue arithmetic circuit is effectively employed as the basic module, and an efficient error detection/correction algorithm in which error detection is performed in each basic module and error correction is performed based on the parallelism of residue arithmetic is also employed. In this case, the error correcting circuit is imposed in series to non-redundant system. This design method has an advantage of compact hardware. Following the proposed method, a 2nd-order recursive fault-tolerant digital filter is practically implemented, and its fault-tolerant ability is proved by noise injection testing.

• 한국통신학회논문지
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• 제21권5호
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• pp.1345-1359
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• 1996

This paper presents a floating point arithmetic unit (FPAU) for supescalar microprocessor that executes fifteen operations such as addition, subtraction, data format converting, and compare operation using two pipelined arithmetic paths and new rounding and normalization scheme. By using two pipelined arithmetic paths, each aritchmetic operation can be assigned into appropriate arithmetic path which high speed operation is possible. The proposed normalization an rouding scheme enables the FPAU to execute roundig operation in parallel with normalization and to reduce timing delay of post-normalization. And by predicting leading one position of results using input operands, leading one detection(LOD) operation to normalize results in the conventional arithmetic unit can be eliminated. Because the FPAU can execuate fifteen single-precision or double-precision floating-point arithmetic operations through three-stage pipelined datapath and support IEEE standard 754, it has appropriate structure which can be ingegrated into superscalar microprocessor.