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http://dx.doi.org/10.6109/jkiice.2017.21.4.774

Design of High Speed Binary Arithmetic Encoder for CABAC Encoder  

Park, Seungyong (Department of Information Communication Engineering, Hanbat National University)
Jo, Hyungu (Department of Information Communication Engineering, Hanbat National University)
Ryoo, Kwangki (Department of Information Communication Engineering, Hanbat National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.21, no.4, 2017 , pp. 774-780 More about this Journal
Abstract
This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.
Keywords
H.264/AVC; HEVC; CABAC; Binary Arithmetic Encoder; Entropy Coding;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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