• 드라이브 ㆍ 컨트롤
• /
• 제15권4호
• /
• pp.30-38
• /
• 2018

Electronic control units (ECUs) are currently popular, and have evolved further towards the high-end application of autonomous vehicles in the automotive industry. Such digital technologies have also become widespread, in agriculture and construction equipment. Likewise, transmission control of high-speed tracked vehicles is based on the transmission control unit (TCU), performing complex gear change control functions, and diagnostic algorithms (a TCU's self-diagnostic and reporting capability of malfunction data through CAN communication). Since all functions of TCU are implemented by embedded-software, it is hardly possible to analyze specifications by reverse engineering. In this paper a real-time transmission simulator adaptable to TCU is presented, for analysis of diagnosis algorithm and standards. Signal simulation circuits are deliberately designed considering electrical characteristics of TCU inputs and various analysis tools, such as analog input auto scan function, and global output enable switch, are implemented in software. Test results from hardware-in-the-loop simulator verify tolerance time for each error, as well as cause of fault, error reset conditions.

• 센서학회지
• /
• 제23권5호
• /
• pp.332-336
• /
• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.

• 한국컴퓨터정보학회논문지
• /
• 제16권5호
• /
• pp.61-71
• /
• 2011

금속물체의 피로도를 측정하기 위하여 고속으로 진동시키면서 비접촉으로 정밀하게 변위를 측정하는 방법에 대한 연구가 많이 이루어지고 있다. 비접촉 고속 진동 검출센서들은 와류 센서나 레이저 센서들을 주로 사용하고있지만 매우 고가이다. 최근 저가의 유도성 센서를 고속 진동검출에 적용하려는 연구가 이루어지고 있으나 아직은 초보단계이다. 본 연구에서는 저가의 유도성 센서를 이용하여 비접촉으로 고속 진동을 검출하는 새로운 근접 센서모듈 설계방법을 제안하였다. 기존의 유도성 센서모듈들은 검파, 적분, 및 증폭과정을 통하여 변위를 검출하기 때문에 아날로그회로 특성상 잡음에 약하고 적분과정에서 변위 검출속도 저하의 요인이 된다. 제안된 방법은 AD변환기(Analog to Digital converter)를 사용하지 않고 진동 주파수신호를 직접 디지털 신호로 변환하는 새로운 방법으로 아날로그 잡음의 영향을 적게 받으며 고속으로 신호를 처리할 수 있는 장점이 있다. 성능 평가를 위하여 셰이커로 진동 주파수를 30Hz부터 1,100Hz 까지 일정간격으로 금속편을 진동시키면서 제안된 센서 모듈을 이용하여 비접촉으로 진동 신호를 검출하였다. 실험결과 비접촉 근접 거리 5mm 이내에서 진동 주파수 검출범위는 DC에서 1,100Hz까지 측정할 수 있었으며 진동 폭의 해상도는 $20{\mu}m$로 나타났다. 따라서 제안된 유도성 센서모듈은 정밀 비접촉 고속 진동검출 센서로서 충분한 성능을 가지고 있다고 평가된다.

• 한국전자통신학회논문지
• /
• 제14권6호
• /
• pp.1145-1152
• /
• 2019

본 논문에서는 디지털 회로와 저소비전력 및 고속연산의 장점을 가진 아날로그 회로를 혼용하기 위하여, 저전력 전류모드 12비트 ADC(: Analog to Digital Converter)를 제안하였다. 제안하는 12비트 ADC는 4비트 ADC의 cascade 구조를 사용하여 소비전력을 줄일 수 있었으며, 변환 current mirror 회로를 사용해 칩면적을 줄일 수 있었다. 제안된 ADC는 매그나칩/SK하이닉스 350nm 공정으로 구현하였고, Cadence MMSIM을 사용하여 post-layout simulation를 진행하였다. 전원전압 3.3V에서 동작하고, 면적은 318㎛ x 514㎛를 차지하였다. 또한 제안하는 ADC는 평균 소비전력 3.4mW의 저소비전력으로 동작하는 가능성을 나타내었다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권6호
• /
• pp.622-634
• /
• 2013

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

• Progress in Superconductivity
• /
• 제7권2호
• /
• pp.109-113
• /
• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• 한국항행학회논문지
• /
• 제20권6호
• /
• pp.612-616
• /
• 2016

감마선이 존재하는 시설물에서는 발생 즉시 이를 발견하여 처리해야 하며 이와 관련하여 무작위적으로 발생하는 신호를 처리하는 소프트웨어적인 방법을 사용하기도 하나 소프트웨어의 메모리 용량과 처리시간이 커지게 된다. 한편 하드웨어적인 방법으로 신호처리할 수 있는 회로가 일반화되어 있으나 발생 신호의 크기가 미약하고 속도가 고속인 경우에는 이에 대응하지 못한다. 하드웨어적으로 효과적으로 신호처리하려면 값이 매우 비싼 부품과 복잡한 회로를 필요로 한다. 따라서 본 연구에서는 크기는 미약하지만 속도가 고속인 감마선 발생신호에 대해서 하드웨어적으로 간단한 피크홀드 회로를 개발하여 피크 시점에서 ADC가 신호값을 직접 읽어냄으로써 감마선 신호의 피크치를 검출하는 회로를 연구, 개발하였다. 이러한 방법으로 하면 복잡한 소프트웨어 신호처리 방법을 사용하지 않고도 고속 발생신호를 효과적으로 포착할 수 있으므로 감마선의 존재가 농후한 방사능 환경에서 이를 사용하기에 적합하다.

• ETRI Journal
• /
• 제32권2호
• /
• pp.265-272
• /
• 2010

To supply a power distribution network with stable power in a high-speed mixed mode system, simultaneous switching noise caused at the multilayer PCB and package structures needs to be sufficiently suppressed. The uni-planar compact electromagnetic bandgap (UC-EBG) structure is well known as a promising solution to suppress the power noise and isolate noise-sensitive analog/RF circuits from a noisy digital circuit. However, a typical UC-EBG structure has several severe problems, such as a limitation in the stop band's lower cutoff frequency and signal quality degradation. To make up for the defects of a conventional EBG structure, a partially located EBG structure with decoupling capacitors is proposed in this paper as a means of both suppressing the power noise propagation and minimizing the effects of the perforated reference plane on the signal quality. The proposed structure is validated and investigated through simulation and measurement in both frequency and time domains.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권2호
• /
• pp.127-138
• /
• 2013

The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of $VIP_2$ and $VIP_3$. The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.

• ETRI Journal
• /
• 제29권4호
• /
• pp.421-429
• /
• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.