• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.12
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• pp.8643-8648
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• 2015

In this paper presents the design and demonstrate 8 W 3-stage HPA(High Power Amplifier) MMIC(Monolithic Microwave Integrated Circuits) for Ka-band down link satellite communications payload system at 19.5 GHz ~ 22 GHz frequency band. The HPA MMIC consist of 3-stage GaN HEMT(Hight Electron Mobility Transistors). The gate periphery of $1^{st}$ stage, $2^{nd}$ stage and output stage is determined $8{\times}50{\times}2$ um, $8{\times}50{\times}4$ um and $8{\times}50{\times}8$ um, respectively. The fabricated HPA MMIC shows size $3,400{\times}3,200um^2$, small signal gain over 29.6 dB, input matching -8.2 dB, output matching -9.7 dB, output power 39.1 dBm and PAE 25.3 % by using 0.15 um GaN technology at 20 V supply voltage in 19.5~22 GHz frequency band. Therefore, this HPA MMIC is believed to be adaptable Ka-band satellite communication payloads down link system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.14-21
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• 2011

A 10b 500MS/s $0.13{\mu}m$ CMOS ADC is proposed for 4G wireless communication systems such as a LTE-Advanced and SDR The ADC employs a calibration-free single-channel folding architecture for low power consumption and high speed conversion rate. In order to overcome the disadvantage of high folding rate, at the fine 7b ADC, a cascaded folding-interpolating technique is proposed. Further, a folding amplifier with the folded cascode output stage is also discussed in the block of folding bus, to improve the bandwidth limitation and voltage gain by parasitic capacitances. The chip has been fabricated with $0.13{\mu}m$ 1P6M CMOS technology, the effective chip area is $1.5mm^2$. The measured results of INL and DNL are within 2.95LSB and l.24LSB at 10b resolution, respectively. The SNDR is 54.8dB and SFDR is 63.4dBc when the input frequency is 9.27MHz at sampling frequency of 500MHz. The ADC consumes 150mW($300{\mu}W/MS/s$) including peripheral circuits at 500MS/s and 1.2V(1.5V) power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.98-106
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• 2009

This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.41 no.11
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• pp.891-899
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• 2013

This paper suggests a test and evaluation procedure of conformal load-bearing antenna structure(CLAS) for high speed military jet application. A log periodic patch type antenna was designed for multi-band communication and navigation antenna. Carbon/Glass fiber reinforced polymer was used as a structure supporting aerodynamic loads and honeycomb layer was used to improve antenna performance. Multi-layers were stacked and cured in a hot temperature oven. Gain, VSWR and polarization pattern of CLAS were measured using anechoic chamber within 0.15~2.0 GHz frequency range. Tension, shear, fatigue and impact load test were performed to evaluate structural strength of CLAS. Antenna performance test after every structural strength test was conducted to check the effect of structural test to antenna performance. After the application of new test and evaluation procedure to validate a new CLAS, a design improvement was found.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3587-3593
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• 2009

Nowadays, the PV systems have been focused on the interconnection between the power source and the grid. The PV inverter, either single-phase or three-phase, can be considered as the core of the whole system because of an important role in the grid-interconnecting operation. An important issue in the inverter control is the load current regulation. In the literature, the Proportional+Integral (PI) controller, normally used in the current-controlled Voltage Source Inverter (VSI), cannot be a satisfactory controller for an ac system because of the steady-sate error and the poor disturbance rejection, especially in high-frequency range. By comparison with the PI controller, the Proportional+Resonant (PR) controller can introduce an infinite gain at the fundamental ac frequency; hence can achieve the zero steady-state error without requiring the complex transformation and the dq-coupling technique. In this paper, a PR controller is designed and adopted for replacing the PI controller. Based on the theoretical analyses, the PR controller based control strategy is implemented in a 32-bit fixed-point TMS320F2812 DSP and evaluated in a 3kW experimental prototype Photovoltaic (PV) power conditioning system (PCS). Simulation and experimental results are shown to verify the performance of implemented control scheme in PV PCS.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.8
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• pp.2968-2974
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• 2010

Nowadays, the PV systems have been focused on the grid connection between the power source and the grid. The PV inverter can be considered as the core of the whole system because of an important role in the grid-interfacing operation. An important issue in the inverter control is the load current regulation. In the literature, Proportional Integral (PI) controller, which is normally used in the current-controlled Voltage Source Inverter (VSI), cannot be a satisfactory controller for an AC system because of the steady-sate error and the poor disturbance rejection, especially in high-frequency range. Compared with conventional PI controller, Proportional Resonant (PR) controller can introduce an infinite gain at the fundamental frequency of the AC source; hence it can achieve the zero steady-state error without requiring the complex transformation and the de-coupling technique. Theoretical analyses of both PI and PR controller are presented and verified by simulation and experiment. Both controller are implemented in a 32-bit fixed-point TMS320F2812 DSP processor and evaluated on a 3kW experimental prototype PV Power Conditioning System (PCS). Simulation and experimental results are shown to verify the controller performances.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.126-142
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• 2016

This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.