Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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An 1.2V 10b 500MS/s Single-Channel Folding CMOS ADC

1.2V 10b 500MS/s 단일채널 폴딩 CMOS A/D 변환기

  • Moon, Jun-Ho (Dongguk University-Seoul, Dept. of Semiconductor Science) ;
  • Park, Sung-Hyun (Dongguk University-Seoul, Dept. of Semiconductor Science) ;
  • Song, Min-Kyu (Dongguk University-Seoul, Dept. of Semiconductor Science)
  • 문준호 (동국대학교-서울, 반도체과학과) ;
  • 박성현 (동국대학교-서울, 반도체과학과) ;
  • 송민규 (동국대학교-서울, 반도체과학과)
  • Received : 2010.04.27
  • Accepted : 2010.12.24
  • Published : 2011.01.25
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Abstract

A 10b 500MS/s $0.13{\mu}m$ CMOS ADC is proposed for 4G wireless communication systems such as a LTE-Advanced and SDR The ADC employs a calibration-free single-channel folding architecture for low power consumption and high speed conversion rate. In order to overcome the disadvantage of high folding rate, at the fine 7b ADC, a cascaded folding-interpolating technique is proposed. Further, a folding amplifier with the folded cascode output stage is also discussed in the block of folding bus, to improve the bandwidth limitation and voltage gain by parasitic capacitances. The chip has been fabricated with $0.13{\mu}m$ 1P6M CMOS technology, the effective chip area is $1.5mm^2$. The measured results of INL and DNL are within 2.95LSB and l.24LSB at 10b resolution, respectively. The SNDR is 54.8dB and SFDR is 63.4dBc when the input frequency is 9.27MHz at sampling frequency of 500MHz. The ADC consumes 150mW($300{\mu}W/MS/s$) including peripheral circuits at 500MS/s and 1.2V(1.5V) power supply.

본 논문에서는 LTE-Advanced, Software defined radio(SRD)등 4G 이동통신 핵심기술에 응용 가능한 10b 500MS/s $0.13{\mu}m$ CMOS A/D 변환기(ADC)를 제안한다. 제안하는 AD는 저전력 특성을 만족하기 위해 특별한 보정기법을 포함하지 않는 단일 채널 형태로 설계되었으며, 500MS/s의 고속 변환속도를 만족하기 위해 폴딩 신호처리 기법을 사용하였다. 또한 하위 7b ADC의 높은 folding rate(FR)을 극복하기 위해 cascaded 형태의 폴딩 인터폴레이팅 기법을 적용하였으며, 폴딩 버스에서 발생하는 기생 커패시턴스에 의한 주파수 제한 및 전압이득 감소를 최소화하기 위해 folded cascode 출력단을 갖는 폴딩 증폭기를 설계하였다. 제안하는 ADC는 $0.13{\mu}m$ lP6M CMOS 공정으로 설계되었으며 유효면적은 $1.5mm^2$이다. 시제품 ADC의 INL, DNL은 10b 해상도에서 각각 2.95LSB, 1.24LSB 수준으로 측정되었으며, 입력주파수 9.27MHz, 500MHz의 변환속도에서 SNDR은 54.8dB, SFDR은 63.4dBc의 특성을 보인다. 1.2V(1.5V)의 전원전압에서 주변회로를 포함한 전체 ADC의 전력소모는 150mW ($300{\mu}W/MS/s$)이다.

Keywords

References

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