• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1396-1401
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• 2004

In recent years, robot has been used widely in industrial field and has been expanded as a result of continous research and development for high-speed and miniaturization. The goal of this paper is to design the special serial manipulator through the understanding of the structure, mobility, and analysis of serial manipulator. Thereafter we control the position and orientation of end-effector with respect to time. In general, a structure of industrial robot consists of several links connected in series by various types of joints. Typically revolute and prismatic joints. The movement of these joints is determined in inverse kinematic analysis. Compared to the complicated structure of parallel and hybrid robot, open loop system retains the characteristic that each link is independent and is controlled easily by AC servomotor that is used to place the robot end-effector toward the accurate point with the desired speed and power while it is operated by position control algorithm. The robot end-effector should trace the given trajectory within the appropriate time. The trajectory of 3D end-effector model made by OpenGL can be displayed on the monitor program simultaneously

• Bulletin of the Korean Space Science Society
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• 2004.10b
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• pp.223-226
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• 2004

This paper presents a feasibility study of an advanced IO board design for the next generation of low-earth orbit satellites. Advanced IO board design includes sensor interface, NO, D/A, Digital Module, Serial Module etc, and allows to process increasing data rates between IO board and CPU board. The higher data rate involved in modem IO board additionally introduce issues such as noise, fault tolerance, command and data handling, limited pin count and power consumption problems. The experience in KOMPSAT-l and 2 program with this kind of problems resulted in using SMCS chip set, a high speed serial link technology based on IEEE-1355 (Space Wire Protocol) (ESA-ESTEC 2003, Parkes 1999), as a standard for next generation of satellite IO board design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.146-153
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• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• Journal of the Korean Society for Precision Engineering
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• v.26 no.8
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• pp.79-88
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• 2009

This paper presents the analytical stiffness analysis method for a low-DOF planar parallel manipulator. An n-DOF (n<3) planar parallel manipulator to which 1- or 2-DOF serial mechanism is connected in series may be used as a positioning device in planar tasks requring high payload and high speed. Differently from a 3-DOF planar parallel manipulator, an n-DOF planar parallel counterpart may be subject to constraint forces as well as actuation forces. Using the theory of reciprocal screws, the planar stiffness is modeled such that the moving platform is supported by three springs related to the reciprocal screws of actuations (n) and constraints (3-n). Then, the spring constants can be precisely determined by modeling the compliances of joints and links in serial chains. Finally, the stiffness of two kinds of 2-DOF planar parallel manipulators with simple and complex springs is analyzed. In order to show the effectiveness of the suggested method, the results of analytical stiffness analysis are compared to those of numerical stiffness analysis by using ADAMS.

• Journal of KIISE:Information Networking
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• v.30 no.4
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• pp.494-503
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• 2003

The IEEE 1394 High Speed Serial Bus is a versatile, high-performance, and low-cost method of promoting interoperability between all types of A/V and computing devices. IEEE 1394 provides two transfer modes: asynchronous mode for best effort service and isochronous mode for best effort service with bandwidth reservation. This paper shows the bus performance and compared the transfer odes first at the link level and then at the application level. For the application level performance, we analyze the bus systems with fixed and adaptive interfaces, applied between the upper layer and the 1394 layer, using polling systems. Also we verifies the analysis models with simulation studies. Based on our analysis, we conclude that the adaptive interface reduces the bus access time and so increases the bus utilization.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Korean Journal of Remote Sensing
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• v.18 no.3
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• pp.147-153
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• 2002

The real-time reception and recording of down-link mission data from a satellite requires the highest reliability because the data lost in receiving process cannot be recovered. The data receiving and recording system has moved from a set of dedicated hardware and software components to commercial-off-the-shelf (COTS) components in order to reduce the system cost as well as to upgrade the system easily for handling other satellite data. The use of COTS hardware and middleware components prevents the system developer from correcting or modifying the internal operations of the COTS components, and hence, instant performance degradation of the COTS components which affects the reliable data acquisition must be covered by a software algorithm. This paper introduces the instant performance problem of a COTS data recording device which leads to the data loss in the real-time data reception and recording process. As a result, the requirement of the modification of the conventional data read/write technique is issued. In order to overcome the data loss problem due to the use of COTS components and the conventional software technique, a new algorithm called a software buffering technique is proposed. The experiments show that the application of the proposed technique results in reliable real-time reception and recording of high speed serial data.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.11
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• pp.1159-1166
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• 2014

In this paper, a resource management scheme for enhancing the network connectivity and reliability in wireless USB system is proposed. Wireless USB protocol is suitable for the application that supports the real-time multimedia service in Ship Area Network since it supports high speed data transfer. However, the device's mobility is caused the dramatic change of link state and network topology, and is occurred the degradation of network performance. Therefore, a resource management scheme for wireless USB system is proposed in this paper. The proposed technique can intelligently treat the change of link state, and solve the degradation of network performance. The simulation results show that proposed protocol can enhance the throughput and delay performance by selecting relay device with better link state.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2000-2003
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• 2003

In recent years, robots have been used widely in industrial field and have been expanded as a result of continuous research and development for high-speed and miniaturization. The goal of this paper is to design the serial manipulator through kinematic analysis and to control the position and orientation of end-effector with respect to time. In general, a structure of industrial robot consists of several links connected in series by various types of joints, typically revolute and prismatic joints. The movement of these joints is determined in inverse kinematic analysis. Compared to the complicated structure of parallel and hybrid robot, open loop system retains the characteristic that each link is independent and is controlled easily. AC servo motor is used to place the robot end-effector toward the accurate point with the desired speed and power while it is operated by position control algorithm. The robot end-effector should trace the given trajectory within the appropriate time. The trajectory of end-effector can be displayed on the monitor of general personal computer through Opengl program.