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Design and Implementation of 8b/10b Encoder/Decoder for Serial ATA  

Heo Jung-Hwa (세명대학교 정보통신학과)
Park Nho-Kyung (호서대학교 정보통신공학과)
Park Sang-Bong (세명대학교 정보통신학과)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.29, no.1A, 2004 , pp. 93-98 More about this Journal
Abstract
Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.
Keywords
Serial ATA; Parallel ATA; 8b/10b encoder; 10b/8b decoder.;
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