• Journal of the Korean Vacuum Society
• /
• v.14 no.1
• /
• pp.29-34
• /
• 2005

The degradation of the SiGe hetero-junction bipolar transistor(HBT) properties in SiGe BiCMOS process was investigated in this paper. The SiGe HBT prepaired by SiGe BiCMOS process, unlike the conventional one, showed the degraded DC characteristics such as the decreased Early voltage, the decreased collector-emitter breakdown voltage, and the highly increased base leakage current. Also, the cutoff frequency(f/sub T/) and the maximum oscillation frequency(f/sub max/) representing the AC characteristics are reduced to below 50%. These deteriorations are originated from the change of the locations of emitter-base and collector-base junctions, which is induced by the variation of the doping profile of boron in the SiGe base due to the high-temperature source-drain annealing. In the result, the junctions pushed out of SiGe region caused the parastic barrier formation and the current gain decrease on the SiGe HBT device.

• Journal of the Korean Vacuum Society
• /
• v.12 no.4
• /
• pp.239-250
• /
• 2003

The reliability degradation phenomena in the SiGe hetero-junction bipolar transistor (HBT) are investigated in this review. In the case of the SiGe HBT the decrease of the current gain, the degradation of the AC characteristics, and the offset voltage are frequently observed, which are attributed to the emitter-base reverse bias voltage stress, the transient enhanced diffusion, and the deterioration of the base-collector junction due to the fluctuation in fabrication process, respectively. The reverse-bias stress on the emitter-base junction causes the recombination current to rise, increasing the base current and degrading the current gain, because hot carriers formed by the high electric field at the junction periphery generate charged traps at the silicon-oxide interface and within the oxide region. Because of the enhanced diffusion of the dopants in the intrinsic base induced by the extrinsic base implantation, the shorter distance between the emitter-base junction and the extrinsic base than a critical measure leads to the reduction of the cut-off frequency ($f_t$) of the device. If the energy of the extrinsic base implantation is insufficient, the turn-on voltage of the collector-base junction becomes low, in the result, the offset voltage appears on the current-voltage curve.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.4
• /
• pp.274-280
• /
• 2007

This paper demonstrates an efficiency improvement of the class E power amplifier (PA) by tuning-out the input capacitance ($C_{IN}$) of the power HBT with a shunt inductance. In order to obtain high output power, the PA needs the large emitter size of a transistor. The larger the emitter size, the higher the parasitic capacitance. The parasitic $C_{IN}$ affects the distortion of the voltage signal at the base node and changes the duty cycle to decrease the PA's efficiency. Adopting the L-C resonance, we obtain a remarkable efficiency improvement of as much as 7%. This PA exhibits output power of 29 dBm and collector efficiency of 71% at 1.9 GHz.

• Journal of electromagnetic engineering and science
• /
• v.5 no.1
• /
• pp.8-13
• /
• 2005

The InGaP/GaAs hetero-junction bipolar transistor(HBT) monolithic voltage-controlled dielectric resonator oscillator(VCDRO) is first demonstrated for a Ku-band low noise block down-converter(LNB) system. The on-chip voltage control oscillator core employing base-collector(B-C) junction diodes is proposed for simpler frequency tuning and easy fabrication instead of the general off-chip varactor diodes. The fabricated VCDRO achieves a high output power of 6.45 to 5.31 dBm and a wide frequency tuning range of ]65 MHz( 1.53 $\%$) with a low phase noise of below -95dBc/Hz at 100 kHz offset and -115 dBc/Hz at ] MHz offset. A]so, the InGaP/GaAs HBT monolithic DRO with the same topology as the proposed VCDRO is fabricated to verify that the intrinsic low l/f noise of the HBT and the high Q of the DR contribute to the low phase noise performance. The fabricated DRO exhibits an output power of 1.33 dBm, and an extremely low phase noise of -109 dBc/Hz at 100 kHz and -131 dBc/Hz at ] MHz offset from the 10.75 GHz oscillation frequency.

• Korean Journal of Materials Research
• /
• v.12 no.6
• /
• pp.470-475
• /
• 2002

The effects of the conditions of the collector formation on electrical characteristics of the packaged SiGe hetero-junction bipolar transistors (HBT) were investigated. While the DC characteristics of SiGe HBTs such as IV characteristic, forward current gain, Early voltage, and breakdown voltage were hardly changed after packaging, the AC characteristics such as $f_{\tau}\; and\; f_{max}$ were degraded severely. With the rise of the collector concentration, the break-down voltage decreased but the $f_{\tau}$ increased. Additionally, $\beta$ and $f_{\tau}$ values were kept high in the range of elevated collector current due to the increase of the critical current density for the onset of the Kirk effect. The devices As implanted before the collector deposition showed lower breakdown voltage and higher $f_{\tau}$ than the others, which seems to be originated from the As up-diffusion resulting in the thinner collector.

• Proceedings of the KAIS Fall Conference
• /
• 2004.06a
• /
• pp.62-64
• /
• 2004

초고속 RF IC의 핵심소자인 SiGe에피텍시층을 가진 이종양극트란지스터 (hetero junction bipolar transistor: HBT)를 0.35um급 CMOS공정으로 제작하였다. 이때 IOW $V_{BE}$영역에서의 Current Gain의 선형성을 향상시키기 위하여 Capping 실리콘의 두께를 200과 300${\AA}$으로 나누고 EDR (Emitter Drive-in RTA)의 온도와 시간을 900$\~$1000C, 0$\~$30sec로 각각 변화시키면서 최적조건을 알아보았다. 실험범위 내에서의 최적공정조건은 300${\AA}$의 capping 실리콘과 975C-30sec의 EDR조건이었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.9
• /
• pp.897-903
• /
• 2011

This paper presents a highly linear power amplifier MMIC, having an output power level of about 1 watt, based on InGaP/GaAs hetero-junction bipolar transistor(HBT) technology for the 900 MHz band. The active bias circuit is applied to minimize the effect of temperature variation. Ballast resistors are optimized to prevent a current collapse and a thermal runaway. The fabricated power amplifier exhibited a gain of 17.6 dB, an output P1dB of 30 dBm, and a PAE of 44.9 % at an output P1dB from the one-tone excitation. It also showed a very high OIP3 of 47.3 dBm at an average output power of 20 dBm from the two-tone excitation.

• Journal of the Korean Vacuum Society
• /
• v.14 no.4
• /
• pp.229-237
• /
• 2005

The degradation phenomena in SiGe hetero-junction bipolar transistors(SiGe HBTs) induced by bias stress are investigated in this review. If SiGe HBTs are stressed over a specific time interval, the device parameters deviate from their nominal values due to the internal changes in the devices. Reverse-bias stress on emitter-base(EB) junctions causes base current increase and current gain decrease because carriers accelerated by the electrical field generate recombination centers. When forward-bias current stress is conducted at an ambient temperature above $140^{\circ}C$ , hot carriers produced by Auger recombination or avalanche multiplication induce current gain fluctuation. Mixed-mode stressing, where high emitter current and high collector-base voltage are simultaneously applied to the device, provokes base current rise as EB reverse-bias stressing does.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.5 no.4
• /
• pp.367-370
• /
• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

• Journal of electromagnetic engineering and science
• /
• v.6 no.2
• /
• pp.92-97
• /
• 2006

In this paper, a fully integrated Ku-band tripler differential MMIC voltage controlled oscillator(VCO), which consists of a differential VCO core and two triplers, is developed using high linearity InGaP/GaAs HBT technology. The VCO core generates an oscillation frequency of 3.583 GHz, an output power of 3.65 dBm, and a phase noise of -96.7 dBc/Hz at 100 kHz offset with a current consumption of 30 mA at a supply voltage of 2.9 V. The tripler shows excellent side band rejection of 23 dBc at 3 V and 12 mA. The tripler differential MMIC VCO produces an oscillation frequency of 10.75 GHz, an output power of -13 dBm and a phase noise of -89.35 dBc/Hz at 100 kHz offset.