• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2045-2049
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• 2008

In this paper, we propose an novel architecture for H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18 um process including SRAM memory.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.114-116
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• 2010

고해상도의 고품질 비디오 서비스가 보편화됨에 따라 최근 초고해상도(UHD: Ultra HD) 비디오 부호화 연구가 진행되고 있으며, 향후 융합환경에서의 HD 및 UHD 비디오를 동시에 제공하기 위하여 초고해상도에 적합한 스케일러블 비디오 부호화도 진행될 것으로 예상된다. 본 논문에서는 UHD/HD 비디오를 제공하기 위한 H.264/SVC의 확장 부호화 기법으로, 현재 표준화가 진행 중인 HEVC(High Efficiency Video Coding)의 대표적인 부호화 툴인 Large Block 개념을 적용한 SVC 부호화 기법을 제시하고 그 성능을 분석한다. 실험결과 Large Block을 적용한 SVC가 기존의 SVC에 비하여 17% 정도의 부호화 이득이 있음을 확인하였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.356-357
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• 2012

본 논문에서는 Full-HD 영상에서 사용되는 H264/AVC의 정수 단위 고속 움직임 예측 방법을 제안한다. 제안되는 알고리즘에서는 다중 해상도 고속 움직임 예측 기법에 기반을 두어 두 계층이 각기 탐색된다. 낮은 해상도의 계층에서는 움직임 벡터 예측자를 중심으로 좁은 탐색 영역을 2 단계로 탐색하여 최적의 점을 찾는다. 높은 해상도의 계층에서는 4 단계로 탐색을 하여 탐색점의 개수를 줄인다. 그리고 두 계층에서 각기 구해진 탐색점들의 비용을 비교하여 매크로블록의 최종 움직임 벡터를 구한다. 시뮬레이션 결과에서는 기존의 연구 결과보다 JM을 기준으로 BD-Rate는 1.55 % 높았고, BD-PSNR은 0.05 dB 낮아진데 비해 시간은 63% 만큼 감소하여 높은 속도를 낼 수 있었다.

• Broadcasting and Media Magazine
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• v.15 no.4
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• pp.9-22
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• 2010

최근 full-HD 3D 방송, UD(ultra-definition) 영상 서비스, mobile device 향 양방향 HD급 화상통신 등 기존 영상 서비스의 품질을 월등히 향상시키고자 하는 연구들이 진행되고 있다. 본 기고에서는 기존 H.264/AVC 영상 압축 표준의 성능을 2배 이상 향상시키는 것을 목표로 진행 중인 새로운 차세대 영상 압축 표준인 HEVC(high-efficiency video coding; MPEG-H/H.265)의 표준화 동향을 소개한다. 또한, 현재 HEVC test-model (HM) version 1을 구성하고 있는 요소 기술들을 결정하기 위해 진행되었던 성능 평가 과정에 대해 간략하게 소개하고, 마지막으로 HM의 전반적 구성 및 현재 성능 수준에 대한 평가결과를 보인다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.106-111
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the parallel operations and SAD unit control using pattern information, the proposed IME instruction supports not only full search algorithm but also other fast search algorithms. The hardware size is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP runs at 160MHz with sixteen PEGs and it can handle 1080p@30 frame in real time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• Journal of Internet Computing and Services
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• v.13 no.1
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• pp.57-63
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• 2012

Recently, Development of high-speed internet networks can be a real-time video conference system. SD-quality still images using the software codec system exists, and two-way system with mobile systems, but in most video only send and receive video system. In this study, HD web-cam using the two-way live broadcasts simultaneously in the education system and the mobile system has developed an audible system. In the study using the H.264 standard video compression techniques were applied to high-bandwidth compression technology, smart phones, to develop a streaming server for broadcasting were applied. Video sharing, document, web-sharing was made possible in real time. In addition, the private IP for WiFi zone, available anytime, anywhere that can be converted to a public IP technology, IP tunneling technology applied.

• Journal of Broadcast Engineering
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• v.13 no.5
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• pp.622-635
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• 2008

Recently, high definition media services like HDTV and IPTV are growing. A fast reduced-size image extracting method is required to meet what those services require. Conventional DC image extracting methods, however, can't be applied to H.264/AVC streams since a spatial domain prediction scheme is adopted in H.264/AVC intra mode. To solve this problem, a thumbnail extraction method in H.264/AVC was proposed. However, the method has mismatch problem which was caused by round-off operation in intra prediction and mismatch between integer and floating point calculation. In this paper, we propose an error compensation method for extracting thumbnail directly in H.264/AVC bitstreams. The compensation method introduces the mismatch problem in thumbnail extraction and presents compensation values. Through the implementation and performance evaluation, proposed method compensated round-off error efficiently in D1 and HD sequences while the additional extraction time is negligible.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.53-60
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• 2009

Motion estimation for H.264/AVC video CODEC is very complex and requires a huge amount of computational efforts because it uses multiple reference frames and variable block sizes. We propose the architecture of high-performance integer-pixel motion estimation circuit based on fast algorithms for multiple reference frame selection, block matching, block mode decision and motion vector estimation. We also propose the architecture of high-performance interpolation circuit for sub-pixel motion estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The integer-pixel motion estimation circuit consists of 77,600 logic gates and four $32\times8\times32$-bit dual-port SRAM's. It has tile maximum operating frequency of 161MHz and can process up to 51 D1 (720$\times$480) color in go frames per second. The fractional motion estimation circuit consists of 22,478 logic gates. It has the maximum operating frequency of 200MHz and can process up to 69 1080HD (1,920$\times$1,088) color image frames per second.

• Journal of IKEEE
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• v.17 no.4
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• pp.418-427
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• 2013

In this paper, we propose a parallel deblocking filter algorithm for H.264/AVC video standard. The deblocking filter has different filter processes according to boundary strength (BS) and each filter process requires various conditional calculations. The order of filtering makes it difficult to parallelize deblocking filter calculations. The proposed deblocking filter algorithm is performed on PRAGRAM which is a 1-D coarse grained reconfigurable architecture (CGRA). Each filter calculation is accelerated using uni-directional pipelined architecture of PRAGRAM. The filter selection and the conditional calculations are efficiently performed using dynamic reconfiguration and conditional reconfiguration. The parallel deblocking filter algorithm uses 225 cycles to process a macroblock and it can process a full HD image at 150 MHz.