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Novel IME Instructions and their Hardware Architecture for Fast Search Algorithm  

Bang, Ho-Il (School of Electrical and Computer Engineering, Ajou University, SoC LAB)
SunWoo, Myung-Hoon (School of Electrical and Computer Engineering, Ajou University, SoC LAB)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.12, 2011 , pp. 58-65 More about this Journal
Abstract
This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.
Keywords
H.264/AVC; video coding; ASIP; reconfigurable coding; motion estimation;
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