Journal of the Institute of Electronics Engineers of Korea SP (대한전자공학회논문지SP)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Motion Estimation Specific Instructions and Their Hardware Architecture for ASIP

ASIP을 위한 움직임 추정 전용 연산기 구조 및 명령어 설계

  • Hwang, Sung-Jo (School of Electrical and Computer Engineering, Ajou University) ;
  • SunWoo, Myung-Hoon (School of Electrical and Computer Engineering, Ajou University)
  • 황성조 (아주대학교 정보통신대학 전자공학부) ;
  • 선우명훈 (아주대학교 정보통신대학 전자공학부)
  • Received : 2010.08.16
  • Accepted : 2010.11.30
  • Published : 2011.05.25
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Abstract

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the parallel operations and SAD unit control using pattern information, the proposed IME instruction supports not only full search algorithm but also other fast search algorithms. The hardware size is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP runs at 160MHz with sixteen PEGs and it can handle 1080p@30 frame in real time.

본 논문은 H.264나 MPEG4등, 다양한 영상압축 코덱을 지원할 수 있는 ME ASIP의 전용 IME 명령어와 재구성 가능한 하드웨어 구조를 제안한다. 제안하는 전용의 명령어와 하드웨어 가속기는 HD급의 고화질 영상을 지원할 수 있는 성능을 가지고 있다. 제안하는 IME명령어는 다수의 병렬 연산과 패턴 정보를 이용한 연산기 제어를 통하여 전역탐색을 비롯한 각종 고속 탐색 알고리즘을 지원한다. 제안한 하드웨어 구조는 256개의 Processor Elements로 구성되어 있는 Processor Element Group (PEG) 하나당 77,860 게이트를 가진다. 16개의 PEG로 구성된 ASIP은 160MHz의 동작 주파수를 가지고 있으며, HD급 1080p의 해상도를 가지는 영상을 실시간으로 동작 시킬 수 있다.

Keywords

References

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