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Design of High-Performance Motion Estimation Circuit for H.264/AVC Video CODEC  

Lee, Seon-Young (Department of Electronics and Information Engineering, Hankuk University of Foreign Studies)
Cho, Kyeong-Soon (Department of Electronics and Information Engineering, Hankuk University of Foreign Studies)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.7, 2009 , pp. 53-60 More about this Journal
Abstract
Motion estimation for H.264/AVC video CODEC is very complex and requires a huge amount of computational efforts because it uses multiple reference frames and variable block sizes. We propose the architecture of high-performance integer-pixel motion estimation circuit based on fast algorithms for multiple reference frame selection, block matching, block mode decision and motion vector estimation. We also propose the architecture of high-performance interpolation circuit for sub-pixel motion estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The integer-pixel motion estimation circuit consists of 77,600 logic gates and four $32\times8\times32$-bit dual-port SRAM's. It has tile maximum operating frequency of 161MHz and can process up to 51 D1 (720$\times$480) color in go frames per second. The fractional motion estimation circuit consists of 22,478 logic gates. It has the maximum operating frequency of 200MHz and can process up to 69 1080HD (1,920$\times$1,088) color image frames per second.
Keywords
H.264/AVC;
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