• Journal of Power Electronics
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• v.17 no.1
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• pp.56-66
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• 2017

Fast and accurate fault detection is the primary step and one of the most important tasks in fault tolerant converters. In this paper, a fast and simple method is proposed to detect and diagnosis the faulty cell in a cascaded H-bridge multilevel inverter under a short circuit fault. In this method, the reference voltage is calculated using switching control pulses and DC-Link voltages. The comparison result of the output voltage and the reference voltage is used in conjunction with active cell pulses to detect the faulty cell. To achieve this goal, the cell which is active when the Fault signal turns to "0" is detected as the faulty cell. Furthermore, consideration of generating the active cell pulses is completely described. Since the main advantage of this method is its simplicity, it can be easily implemented in a programmable digital device. Experimental results obtained with an 11-level inverter prototype confirm the effectiveness of the proposed fault detection technique. In addition, they show that the diagnosis method is unaffected by variations of the modulation index.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.51-59
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.11a
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• pp.123-127
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• 1992

When MOS devices is exposed to radiation, radiation effects of P-type MOS capacitor can cause modulation and/or degradation in devices characteristics and its operating life. The oxide layer is grown in $O_2$+T.C.E. and its thickness ranges from 40 to 80 nm. Irradiations on MOS capacitor were performed by Cobalt-60 gamma ray source and total dose ranges from $10^4$ to $10^8$ rads. The radiation effect on electrical conduction characteristics(I-V) in MOS capacitor was measured as a function of gate oxide thickness and total dose. From the experimental result, I-V characteristics is found to be influenced strongly by total dose in irradiated p-type MOS capacitors. The ohmic current is dependant on of total dose in irradiated P-type MOS capacitors. This results are explained using surface states at interface radiation-induced traps.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.4
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• pp.551-561
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• 2001

In this paper, the large signal unified model is established for H4O GaAs pHEMT of GEC-Marconi using modified Curtice model. This unified model includes DC characteristic, small signal, and noise characteristic as various bias. Particularly, the model can simply and physically explain trans-conductance $(g_m)$ of pHEMT using modified Curtice model, and can tell the difference $g_m$, $R_ds$ at DC and these at AC through inclusion of internal RF-choke. The results of the established model built up using SDD in HP-Eessof show good agreement to the S/W measured data in DC, small signal, and noise characteristic. This model can also be applied to various computer aided analysis, such as linear simulation, 1-tone harmonic balance simulation, and multi-tone harmonic balance simulation, so the LNA(Low Noise Amplifier), oscillator, and mixer design has been shown using this model library.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.4
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• pp.246-250
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• 2021

TFTs technologies with as high mobility as possible is essential for high-performance large displays. TFTs using nanocrystalline silicon thin films can achieve higher mobility. In this work, the change of the crystalline volume fraction at different hydrogen dilution ratios was investigated by depositing nc-Si:H thin films using PECVD. It was observed that increasing hydrogen dilution ratio increased not only the crystalline volume fraction but also the crystallite size. The thin films with a high crystalline volume fraction (55%) and a low defect density (10¹⁷ cm^-3·eV^-1) were used as top gate TFTs channel layer, leading to a high mobility (55 cm²/V·s). We suggest that TFTs of high mobility to meet the need of display industries can be benefited by the formation of thin film with high crystalline volume fraction as well as low defect density as a channel layer.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.431-435
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• 2011

This paper presents optimized searching technique to improve the performance of H.264/AVC. The proposed CAVLC encoder uses forward and backward searching algorithm to compute the parameters. By zero-block skipping technique and pipelined scheduling, the proposed CAVLC encoder can obtain better performance. The experimental result shows that the proposed architecture needs only 66.6 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 13.8% than that of previous designs. The proposed CAVLC encoder was implemented using VerilogHDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 15.6K with 125Mhz clock frequency.

• KIEE International Transactions on Power Engineering
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• v.3A no.3
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• pp.148-154
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• 2003

This paper describes the development of KEPCO's 80MVA UPFC electromagnetic transient model and the analysis of its performance in the actual Korean power system. KEPCO's 80MVA UPFC is currently undergoing installation and will be ready for commercial operation from the year 2003. In order to apply a new FACTS device such as the UPFC to the actual power system, the utility needs, in advance, both load flow stability studies and transient studies. Therefore, KEPRI, the research institute of KEPCO, developed a detailed transient analysis model that is based on the actual UPFC S/W algorithm and H/W specifications. This simulation model is implemented by an EMTDC/PSCAD package. The results of the simulation show the effectiveness of UPFC operation in the KEPCO power system.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2009.10a
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• pp.103-107
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• 2009

Recently, injection/compression molding process became more popular than ever to produce many transparent optical products of high precision. Especially, optical disk for read/write is the best example. But those optical disks can cause sensorial problems because of high birefringence or deformation from the residual stresses in the media. Therefore, it is necessary to study the effects of various process conditions on the final birefringence structure in injection-only and injection/compression molded disks for producing precision injection-molded products. In the present paper we have focused on the effect of injection, holding and compression processes on the optical anisotropy(i.e. birefringence) remaining in the MOD by examining the gapwise distribution of birefringence and extinction angle. The effect of holding pressure was found to form the inner two birefringence peaks. But the effect of compression pressure on the birefringence distribution was found to make the uniform distribution near the center in the gapwise direction and inversion of extinction angle far from the gate.